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| doc. no. 100475a october 28, 1999 6 p d u w + & ) ? 0 r e l o h 0 r g h p + r v w & r q w u roo h g 9 . i o h [ ? 0 r g h p 'h y l f h 6 h w z l w k + r v w 6 l g h 'h y l f h 3 6 p d u w ' $$ ? d q g 2 s w l r q d o 9 r l f h & r g h f i r u 3 & , % x v 0 l q l 3 & , & d u g % x v % d v h g 0 r e l o h $ ss o l f d w l r q v ' h v l j q h u } v * x l g h 3 u h o l p l q d u \ conexant proprietary information
SMARTHCF mobile modem designers guide ii conexant 100475a conexant proprietary information information provided by conexant systems, inc. is believed to be accurate and reliable. however, no responsibility is assumed b y conexant for its use, nor any infringement of patents, copyrights, or other rights of third parties which may result from its use. no li cense is granted by implication or otherwise under any patent rights or copyright of conexant other than for circuitry embodied in conexant product s. conexant reserves the right to change circuitry at any time without notice. this document is subject to change without notice. conexant products are not designed or intended for use in life support appliances, devices, or systems where malfunction of a conexant product can reasonably be expected to result in personal injury or death. conexant customers using or selling conexant products for use in such applications do so at their own risk and agree to fully indemnify conexant for any damages resulting from such improper us e or sale. k56flex is a trademark of conexant systems, inc. and lucent technologies. conexant, the conexant c symbol, what's next in communications technologies, smartdaa, SMARTHCF, and smarthsf are trademarks of conexant systems, inc. product names or services listed in this publication are for identification purposes only, and may be trademarks or registered trademarks of third parties [their respective companies]. all other marks mentioned herein are the property of their respective [holders] own ers. ?1999, conexant systems, inc. all rights reserved SMARTHCF mobile modem designers guide 100475a conexant iii conexant proprietary information table of contents 1. introduction................................................................................................................. ................................ 1-1 1.1 overview .................................................................................................................... .......................... 1-1 1.2 features .................................................................................................................... .......................... 1-4 1.2.1 general modem features .................................................................................................... ...... 1-4 1.2.2 pci bus host interface features ........................................................................................... .... 1-4 1.2.3 smartdaa features ......................................................................................................... .......... 1-5 1.2.4 applications.............................................................................................................. .................. 1-5 1.3 technical overview.......................................................................................................... ............... 1-5 1.3.1 general description ....................................................................................................... ............ 1-5 1.3.2 host modem software....................................................................................................... ......... 1-5 1.3.3 operating modes........................................................................................................... ............. 1-5 data/fax modes................................................................................................................ 1 -5 synchronous access mode (sam) - video conferencing................................................. 1-6 tam mode....................................................................................................................... .. 1-6 voice/speakerphone mode (s models) ............................................................................ 1-6 1.3.4 reference design .......................................................................................................... ............ 1-6 1.4 hardware description ........................................................................................................ ........... 1-6 1.4.1 host side device (hsd).................................................................................................... ......... 1-6 1.4.2 digital isolation barrier (dib) (oem supplied) ........................................................................... 1 -7 1.4.3 smartdaa line side device (lsd)........................................................................................... .1-7 1.4.4 voice codec (vc) (s models) ............................................................................................... ..... 1-7 2. technical specifications ..................................................................................................... ................... 2-1 2.1 establishing data modem connections................................................................................... 2-1 dialing ........................................................................................................................ ....... 2-1 modem handshaking protocol .......................................................................................... 2-1 call progress tone detection ........................................................................................... 2-1 answer tone detection..................................................................................................... 2-1 ring detection................................................................................................................. .. 2-1 billing protection ............................................................................................................. .. 2-1 connection speeds........................................................................................................... 2-1 automode....................................................................................................................... ... 2-1 2.2 data mode ................................................................................................................... ......................... 2-1 speed buffering (normal mode) ....................................................................................... 2-1 dte-to-modem flow control............................................................................................. 2-1 escape sequence detection............................................................................................. 2-1 gstn cleardown (v.90/k56flex, v.34, v.32 bis, v.32)..................................................... 2-2 fall forward/fallback (v.90/k56flex, v.34/v.32 bis/v.32) ................................................ 2-2 retrain........................................................................................................................ ....... 2-2 2.3 error correction and data compression............................................................................. 2-2 v.42 error correction ........................................................................................................ 2- 2 mnp 2-4 error correction ................................................................................................. 2-2 v.42 bis data compression .............................................................................................. 2-2 mnp 5 data compression ................................................................................................ 2-2 2.4 fax class 1 operation....................................................................................................... .............. 2-2 2.5 voice/tam mode .............................................................................................................. .................... 2-2 2.5.1 online voice command mode ................................................................................................. .. 2-2 2.5.2 voice receive mode ........................................................................................................ .......... 2-3 2.5.3 voice transmit mode ....................................................................................................... .......... 2-3 2.5.4 speakerphone modes ........................................................................................................ ........ 2-3 2.6 full-duplex speakerphone (fdsp) mode .................................................................................. 2-3 2.7 caller id................................................................................................................... ............................ 2-3 2.8 multiple country support (w models) .................................................................................... 2-3 2.8.1 oem programmable parameters ............................................................................................... 2-3 2.8.2 blacklist parameters ...................................................................................................... ............ 2-4 SMARTHCF mobile modem designers guide iv conexant 100475a conexant proprietary information 2.9 diagnostics................................................................................................................. ........................ 2-4 2.9.1 commanded tests........................................................................................................... .......... 2-4 2.10 low power sleep mode....................................................................................................... ............ 2-4 3. hardware interface ........................................................................................................... ...................... 3-1 3.1 hsd (p9573) hardware pins and signals .................................................................................... 3-1 3.1.1 hsd signal interfaces..................................................................................................... ........... 3-1 pci bus/minipci/cardbus host interface ......................................................................... 3-1 power detection and switching ........................................................................................ 3-1 serial eeprom interface ................................................................................................. 3-1 lsd interface (through dib) ............................................................................................ 3-2 vc interface (s models).................................................................................................... 3-2 telephone handset interface (s models) ......................................................................... 3-2 call progress speaker interface ....................................................................................... 3-2 3.1.2 hsd interface signals, pin assignments, and signal definitions .............................................. 3-2 3.2 lsd (20463) hardware pins and signals................................................................................... 3-11 3.2.1 lsd signal interfaces ..................................................................................................... ......... 3-11 hsd interface (through dib).......................................................................................... 3-11 telephone line interface ................................................................................................ 3-11 3.2.2 lsd interface signals, pin assignments, and signal definitions............................................. 3-11 3.3 vc (20437) hardware pins and signals (s models) ............................................................... 3-16 3.3.1 vc signal interfaces ...................................................................................................... .......... 3-16 speakerphone interface.................................................................................................. 3-16 telephone handset/headset interface ........................................................................... 3-16 hsd interface.................................................................................................................. 3-16 3.3.2 vc interface signals, pin assignments, and signal definitions............................................... 3-16 3.4 electrical, environmental, and timing specifications................................................... 3-22 3.4.1 operating conditions and absolute maximum ratings............................................................ 3-22 caution: handling cmos devices .................................................................................. 3-22 3.4.2 pci bus electrical, switching, and timing characteristics............................ 3-22 3.4.3 serial eeprom interface timing ................................................................................. 3-23 4. crystal specifications ....................................................................................................... ................... 4-25 5. layout guidelines............................................................................................................ ........................... 5-1 5.1 emi considerations .......................................................................................................... ................ 5-1 5.1.1 general ................................................................................................................... ................... 5-1 5.1.2 filtering ................................................................................................................. ..................... 5-1 5.1.3 decoupling ................................................................................................................ ................. 5-2 5.1.4 optional configurations ................................................................................................... .......... 5-2 5.2 general layout guidelines for a 2-layer pci board .......................................................... 5-3 5.2.1 placing components ........................................................................................................ .......... 5-3 5.2.2 power ..................................................................................................................... .................... 5-4 5.2.3 grounds ................................................................................................................... .................. 5-4 5.2.4 trace widths.............................................................................................................. ................ 5-4 5.2.5 trace spacing............................................................................................................. ............... 5-4 5.2.6 trace routing ............................................................................................................. ............... 5-5 5.3 specific layout guidelines for a 6-layer mini pci board .................................................. 5-6 5.3.1 digital section ........................................................................................................... ................. 5-6 crystal circuit................................................................................................................ .... 5-6 dib interface .................................................................................................................. ... 5-6 minipci signal routing ..................................................................................................... 5-6 SMARTHCF mobile modem designers guide 100475a conexant v conexant proprietary information 5.3.2 daa section............................................................................................................... ................ 5-6 daa isolation gap............................................................................................................. 5 -6 daa section grounding .................................................................................................... 5-7 dib interface .................................................................................................................. ... 5-7 dc hold and impedance match interface ......................................................................... 5-7 diode bridge ................................................................................................................... .. 5-7 vc and vref circuit ........................................................................................................ 5-7 telephone line interface .................................................................................................. 5-7 handset interface (optional) ............................................................................................. 5-8 5.4 package dimensions.......................................................................................................... ............. 5-11 6. host software interface ...................................................................................................... ................. 6-1 6.1 pci configuration registers................................................................................................. ...... 6-1 6.1.1 0x00 - vendor id field .................................................................................................... ........... 6-2 6.1.2 0x02 - device id field.................................................................................................... ............ 6-2 6.1.3 0x04 - command register ................................................................................................... ...... 6-2 6.1.4 0x06 - status register .................................................................................................... ........... 6-3 6.1.5 0x08 - revision id field.................................................................................................. ........... 6-3 6.1.6 0x09 - class code field................................................................................................... .......... 6-3 6.1.7 0x0d - latency timer register ............................................................................................. ..... 6-3 6.1.8 0x0e - header type field .................................................................................................. ........ 6-3 6.1.9 0x28 - cis pointer register ............................................................................................... ........ 6-3 6.1.10 0x2c - subsystem vendor id register ...................................................................................... 6-4 6.1.11 0x2e- subsystem id register .............................................................................................. ...... 6-4 6.1.12 0x34 - cap ptr ........................................................................................................... ................. 6-4 6.1.13 0x3c - interrupt line register ........................................................................................... ......... 6-4 6.1.14 0x3d - interrupt pin register............................................................................................ .......... 6-4 6.1.15 0x3e - min grant register................................................................................................ .......... 6-4 6.1.16 0x3f - max latency register .............................................................................................. ....... 6-4 6.1.17 0x40 - capability identifier ............................................................................................. ............ 6-4 6.1.18 0x41 - next item pointer ................................................................................................. ........... 6-4 6.1.19 0x42 - pmc - power management capabilities ......................................................................... 6-5 6.1.20 0x44 - pmcsr - power management control/status register (offset = 4)............................... 6-5 6.1.21 0x46 - pmcsr_bse - pmcsr pci to pci bridge support extensions..................................... 6-6 6.1.22 0x47 - data .............................................................................................................. .................. 6-6 6.2 base address register ....................................................................................................... ........... 6-6 6.3 serial eeprom interface ..................................................................................................... .......... 6-7 6.3.1 supported eeprom sizes .................................................................................................... .... 6-7 6.3.2 definitions ............................................................................................................... ................... 6-8 device id register ............................................................................................................ 6 -8 vendor id register............................................................................................................ 6 -8 subsystem vendor id and subsystem device register ................................................... 6-8 min_gnt register .............................................................................................................. 6 -8 max_lat register .............................................................................................................. 6 -9 pmc [8:6] and pme drv type ......................................................................................... 6-9 class code register (class code, sub-class code, prog. i/f) ........................................ 6-9 cardbus cis pointer (cardbus cis pointer high, cardbus cis pointer low).................. 6-9 data register (d3, d2, d1, d0 power consumed and d3, d2, d1, d0 power dissipated).................................................................................................................... ..... 6-9 load cisram count (cis _size) .................................................................................... 6-9 SMARTHCF mobile modem designers guide vi conexant 100475a conexant proprietary information list of figures figure 1-1. SMARTHCF modem simplified interface diagram ........................................................................ ........................... 1-2 figure 1-2. SMARTHCF modem major interfaces.................................................................................... ................................... 1-3 figure 3-1. hsd (p9573) 100-pin tqfp hardware interface signals................................................................ ...................... 3-3 figure 3-2. hsd (p9573) 100-pin tqfp pin signals ............................................................................... ................................ 3-4 figure 3-3. lsd (20463) 32-pin tqfp hardware interface signals................................................................. ...................... 3-12 figure 3-4. lsd (20463) 32-pin tqfp pin signals................................................................................ ................................ 3-12 figure 3-5. vc (20437) 32-pin tqfp hardware interface signals.................................................................. ....................... 3-17 figure 3-6. vc (20437) 32-pin tqfp pin signals................................................................................. ................................. 3-17 figure 3-7. waveforms - serial eeprom interface ................................................................................ ............................... 3-23 figure 5-1. pciclk guard band technique ........................................................................................ .................................... 5-9 figure 5-2. crystal solution ................................................................................................... ................................................... 5-9 figure 5-3. power and ground distribution ...................................................................................... ...................................... 5-10 figure 5-4. bridge connections................................................................................................. ............................................. 5-10 figure 5-5. package dimensions - 100-pin tqfp .................................................................................. ............................... 5-11 figure 5-6. package dimensions - 32-pin tqfp................................................................................... ................................. 5-12 list of tables table 1-1. SMARTHCF modem models and functions ................................................................................. ............................. 1-2 table 3-1. hsd (p9573) 100-pin tqfp pin signals ................................................................................ ................................ 3-5 table 3-2. hsd (p9573) 100-pin tqfp pin signal definitions ..................................................................... ........................... 3-7 table 3-3. lsd (20463) 32-pin tqfp pin signals ................................................................................. ................................ 3-13 table 3-4. lsd (20463) 32-pin tqfp pin signal definitions ...................................................................... ........................... 3-14 table 3-5. lsd (20463) digital electrical characteristics...................................................................... ................................. 3-15 table 3-6. vc (20437) 32-pin tqfp pin signals .................................................................................. ................................. 3-18 table 3-7. vc (20437) 32-pin tqfp pin signal definitions ....................................................................... ............................ 3-19 table 3-8. vc digital electrical characteristics ............................................................................... ....................................... 3-21 table 3-9. vc analog electrical characteristics................................................................................ ..................................... 3-21 table 3-10. operating conditions............................................................................................... ............................................ 3-22 table 3-11. absolute maximum ratings........................................................................................... ...................................... 3-22 table 3-12. timing - serial eeprom interface................................................................................... ................................... 3-23 table 4-1. crystal specifications - surface mount .............................................................................. ................................... 4-25 table 4-2. crystal specifications - through hole ............................................................................... .................................... 4-26 table 6-1. pci configuration registers......................................................................................... ........................................... 6-1 table 6-2. command register .................................................................................................... ............................................. 6-2 table 6-3. status register..................................................................................................... ................................................... 6-3 table 6-4. power management capabilities (pmc) register ........................................................................ ........................... 6-5 table 6-5. power management control/status register (pmcsr).................................................................... ...................... 6-5 table 6-6. hsd address map..................................................................................................... .............................................. 6-6 table 6-7. eeprom content for 256 words by 16 bits per word .................................................................... ....................... 6-7 table 6-8. eeprom content for 128 words by 16 bits per word .................................................................... ....................... 6-7 SMARTHCF mobile modem designers guide 100475a conexant 1-1 conexant proprietary information 1. introduction 1.1 overview the conexant ? SMARTHCF host-controlled, v.90/k56flex modem device family with smartdaa technology supports analog data up to 56 kbps, analog fax to 14.4 kbps, telephone answering machine (tam), voice/speakerphone (optional), and pci bus/minipci/cardbus host interface operation. these modem devices meet the size and power requirements of the mobile environment. the modem operates with pstn telephone lines in the u.s./japan/canada and optionally world-wide. modem software is provided. table 1-1 lists the available models. conexant's smartdaa technology (patent pending) eliminates the need for a costly line transformer, relays, and opto- isolators typically used in discrete daa (data access arrangement) implementations. the smartdaa architecture also simplifies product implementation by eliminating the need for country-specific board configurations enabling world-wide homologation of a single modem board design. the smartdaa system-powered daa operates reliably without drawing power from the line, unlike line-powered daas which operate poorly when line current is insufficient due to long lines or poor line conditions. enhanced features, such as monitoring of local extension status without going off-hook, are also supported. incorporating conexants proprietary digital isolation barrier (dib) design (patent pending) and other innovative daa features, such as digital pbx line protection and reporting, the smartdaa architecture simplifies application design, minimizes layout area, and reduces component cost. for over a decade, conexant has assisted customers with daa technology and homologation. this expertise and system level approach has been leveraged in this product. the SMARTHCF device set, consisting of a host side device (hsd) in a 100-pin tqfp and a line side device (lsd) (smartdaa device) in a 32-pin tqfp, supports data/fax/tam operation with hardware-based digital signal processing and daa/telephone line interface functions (figure 1-1 ). the optional voice codec (vc), in a 32-pin tqfp, supports voice/full- duplex speakerphone (fdsp) operation with interfaces to a microphone, speaker, and telephone handset/headset. figure 1-2 identifies the major hardware signal interfaces. in v.90/k56flex data mode, the modem can receive data at speeds up to 56 kbps from a digitally connected v.90 or k56flex- compatible central site modem. in this mode, the modem can transmit data at speeds up to v.34 rates. in v.34 data mode, the modem operates at line speeds up to 33.6 kbps. when applicable, error correction (v.42/mnp 2-4) and data compression (v.42 bis/mnp 5) maximize data transfer integrity and boost average data throughput. non-error- correcting mode is also supported. fax group 3 send and receive rates are supported up to 14.4 kbps with t.30 protocol. v.80 synchronous access mode supports host-controlled communication protocols, e. g., h.324 video conferencing. audio recording and playback over the telephone line interface using a-law, m -law, or linear coding at 8 khz sample rate supports applications such as remote digital telephone answering machine (tam). this designer's guide describes the modem hardware capabilities and identifies the supporting commands. commands and parameters are defined in the commands reference manual (doc. no. 100498, formerly identified as doc. no. 1118). SMARTHCF mobile modem designers guide 1-2 conexant 100475a conexant proprietary information 7deoh 6pduw+&) 0rghp 0rghov dqg )xqfwlrqv 0rgho2ughu3duw 1xpehuv 6xssruwhg )xqfwlrqv 0dunhwlqj 1dph 'hylfh 6hw 2ughu 1r +rvw 6lgh 'hylfh +6' >3lq 74)3@ 3duw 1r /lqh 6lgh 'hylfh /6' 6pduw'$$ >3lq 74)3@ 3duw 1r 9rlfh &rghf 9& >3lq 74)3@ 3duw 1r +rvw %xv '$$ 7\sh 9 .ioh[ 'dwd 9 )d[ 7$0 :ruog :lgh 9rlfh )'63 6pduw+&)03&, '6/ 3 2 3&, 86-& < 2 2 6pduw+&)063&, '6/ 3 3&, 86-& < 2 < 6pduw+&)0:3&, '6/ 3 2 3&, :: < < 2 6pduw+&)0:63&, '6/ 3 3&, :: < < < 6pduw+&)0&&% '6/ 3 2 &dug%xv 86-& < 2 2 6pduw+&)0&6&% '6/ 3 &dug%xv 86-& < 2 < 6pduw+&)0&:&% '6/ 3 2 &dug%xv :: < < 2 6pduw+&)0&:6&% '6/ 3 &dug%xv :: < < < 1rwhv 0rgho rswlrqv 0 0reloh 6 9rlfhixoogxsoh[ vshdnhuskrqh )'63 : :ruogzlgh &% &dug%xv ,qwhuidfh 3&, 3&,0lql3&, ,qwhuidfh 6xssruwhg ixqfwlrqv < 6xssruwhg 1rw vxssruwhg 7$0 7hohskrqh dqvzhulqj pdfklqh 9rlfh sod\edfn dqg uhfrug wkurxjk whohskrqh olqh )'63 )xoogxsoh[ vshdnhuskrqh dqg yrlfh sod\edfn dqg uhfrug wkurxjk whohskrqh olqh kdqgvhw dqg plfvshdnhu 86-& 86 -dsdq &dqdgd :: :ruogzlgh 6riwzduh frqiljxudwlrqixqfwlrqv ghwhuplqhg e\ 'hylfh ,' ordghg lqwr ((3520 vhh 6hfwlrq host side device (hsd) p9573 100-pin tqfp line side device (lsd) (smartdaa) 20463 32-pin tqfp voice codec (vc) 20437 32-pin tqfp (optional) mic speaker tip ring telephone line interface discrete components md260f1_sid digital isolation barrier (dib) pci bus/ mini pci/ cardbus tip ring handset (optional) telephone line (optional) )ljxuh 6pduw+&) 0rghp 6lpsolilhg ,qwhuidfh 'ldjudp SMARTHCF mobile modem designers guide 100475a conexant 1-3 conexant proprietary information +rvw 6lgh 'hylfh +6' 3 3lq 74)3 9rlfh &rghf 9& 3lq 74)3 2swlrqdo 0lf6shdnhu ,qwhuidfh 2swlrqdo 7,3 5,1* 7hohskrqh /lqh ,qwhuidfh 'lvfuhwh &rpsrqhqwv 7,3 5,1* &rqh[dqw 0rghp 6riwzduh &rqh[dqw 0rghp +dugzduh 'hylfhv &rqh[dqw 0rghp 3urgxfw 6pduw'$$ ,qwhuidfh 3&, %xv 0lql 3&, &dug%xv ,qwhuidfh '63 9rlfh 5hod\ +6 3lfnxs 'hwhfwru 2swlrqdo 7(/(3+21( /,1( 7(/(3+21( +$1'6(7 'ljlwdo 6shdnhu &lufxlw 2swlrqdo 0rghp 6riwzduh 'ulyhuv 2shudwlqj 6\vwhp 6riwzduh dqg 0rghp &rppxqlfdwlrq $ssolfdwlrq 6riwzduh 2(0 6xssolhg +dugzduh 2(0&xvwrphu 6xssolhg 6riwzduh +rvw &rpsxwhu 3&, %xv 0lql 3&, &dug%xv 0,& 63($.(5 0')b),' 6281'8&(5 'ljlwdo ,vrodwlrq %duulhu ',% &rpsrqhqwv 9rlfh &rghf ,qwhuidfh /lqh 6lgh 'hylfh /6' 6pduw'$$ 3lq 74)3 /lqh 6lgh ',% ,qwhuidfh /6', &rghf 7hohskrqh /lqh ,qwhuidfh '$$ +dugzduh +6 +\eulg &rpsrqhqwv 2swlrqdo 5hfwlilhu dqg )lowhu &rpsrqhqwv )ljxuh 6pduw+&) 0rghp 0dmru ,qwhuidfhv SMARTHCF mobile modem designers guide 1-4 conexant 100475a conexant proprietary information 1.2 features 1.2.1 general modem features v.90 data modem with receive rates up to 56k bps and send rates up to v.34 rates - itu-t v.90, k56flex, v.34 (33.6 kbps), v.32 bis, v.32, v.22 bis, v.22, v.23, and v.21; bell 212a and 103 - v.42 lapm and mnp 2-4 error correction - v.42 bis and mnp 5 data compression - v.250 (ex v.25 ter) and v.251 (ex v.25 ter annex a) commands v.17 fax modem with send and receive rates up to 14.4 kbps - v.17, v.29, v.27 ter, and v.21 ch 2 - eia/tia 578 class 1 and t.31 class 1.0 commands telephony/tam - v.253 commands - 8-bit m -law/a-law coding (g.711) - 8-bit/16-bit linear coding - 8 khz sample rate - concurrent dtmf, ring, and caller id detection v.80 synchronous access mode supports host-controlled communication protocols with h.324 interface support v.8/v.8bis and v.251 (ex v.25 ter annex a) commands data/fax/voice call discrimination full-duplex speakerphone (fdsp) mode (s models) - microphone and speaker interface - telephone handset/headset interface hardware-based digital signal processing single configuration profile stored in host operates in us/japan/canada world-wide operation (w models) - complies to tbr21 and other country requirements - caller id detection system compatibilities - windows 95, windows 95 osr2, windows 98, windows nt 4.0, windows 2000 operating systems - microsoft's pc 98 and pc 99 design initiative compliant - advanced configuration and power interface (acpi) - unimodem/v compliant - pentium 133 mhz compatible pc or greater - 16 mbyte ram or more thin packages support low profile designs - hsd (p9573): 100-pin tqfp (1.2 mm max. height) - lsd (20463): 32-pin tqfp (1.6 mm max. height) - vc (20437): 32-pin tqfp (1.6 mm max. height) +3.3v operation with +5v tolerant digital inputs 1.2.2 pci bus host interface features 32-bit pci bus host interface - meets pci local bus specification rev. 2.2 - pci bus mastering interface - 33 mhz pci clock support supports power management - meets pci bus power management spec. rev. 1.1 - acpi power management registers - apm support - pme# support - vaux/vpci power switching support - vauxdet support SMARTHCF mobile modem designers guide 100475a conexant 1-5 conexant proprietary information 1.2.3 smartdaa features digital pbx line protection system side powered daa operates under poor line current supply conditions wake-on-ring ring detection line polarity reversal detection line current loss detection caller id (cid) detection pulse dialing line-in-use detection C detects even while on-hook remote hang-up detect C for efficient call termination extension pickup detect call waiting detection meets world-wide dc vi masks requirements (w models) 1.2.4 applications laptop, notebook, and handheld computers pci bus/mini-pci embedded system boards pci bus/mini-pci/cardbus plug-in cards 1.3 technical overview 1.3.1 general description modem operation, including dialing, call progress, telephone line interface, telephone handset interface, voice/speakerphone interface, and host interface functions are supported and controlled through the v.250, v.251, and v.253-compatible command set. the modem hardware connects to the host processor via a pci/minipci/cardbus bus interface. the oem adds a crystal circuit, eeprom, dib and lsd power rectifier and filter components, telephone line interface, optional telephone handset interface, optional voice/speakerphone interface, and other supporting discrete components as required by the modem model and the application to complete the system. 1.3.2 host modem software the host modem software performs the following tasks: 1. general modem control, which includes command sets, fax class 1, tam, voice/speakerphone, error correction, data compression, and operating system interface functions. 2. modem data pump (mdp) control. binary dsp executable code controlling mdp operation is downloaded as required during operation. signal processing, including data and facsimile modulation and demodulation, as well as voice sample formatting, is performed in the hardware dsp. 3. smartdaa control, which includes hsd smartdaa interface control, lsd configuration and control, telephone line interface parameter control, and telephone line impedance control. configurations of the modem software are provided to support modem models listed in table 1-1. 1.3.3 operating modes data/fax modes in v.90/k56flex data modem mode, the modem can receive data from a digital source using a v.90- or k56flex-compatible central site modem at line speeds up to 56 kbps. asymmetrical data transmission supports sending data at line speeds up to v.34 rates. this mode can fallback to full-duplex v.34 mode, and to lower rates, as dictated by line conditions. in v.34 data modem mode, the modem can operate in 2-wire, full-duplex, asynchronous modes at line rates up to 33.6 kbps. data modem modes perform complete handshake and data rate negotiations. using v.34 modulation to optimize modem configuration for line conditions, the modem can connect at the highest data rate that the channel can support from 33600 bps down to 2400 bps with automatic fallback. automode operation in v.34 is provided in accordance with pn3320 and in v.32 bis in accordance with pn2330. all tone and pattern detection functions required by the applicable itu or bell standard are supported. in v.32 bis data modem mode, the modem can operate at line speeds up to 14.4 kbps. SMARTHCF mobile modem designers guide 1-6 conexant 100475a conexant proprietary information in fax modem mode, the modem can operate in 2-wire, half-duplex, synchronous modes and can support group 3 facsimile send and receive speeds of 14400, 12000, 9600, 7200, 4800, and 2400 bps. fax data transmission and reception performed by the modem are controlled and monitored through the eia/tia-578 class 1 or t.31 class 1.0 command interface. full hdlc formatting, zero insertion/deletion, and crc generation/checking are provided. synchronous access mode (sam) - video conferencing v.80 synchronous access mode between the modem and the host/dte is provided for host-controlled communication protocols, e.g., h.324 video conferencing applications. voice-call-first (vcf) before switching to a videophone call is also supported. tam mode tam mode features include 8-bit m -law, a-law, and linear coding at 8 khz sample rate. full-duplex voice supports concurrent voice receive and transmit. tone detection/generation, call discrimination, and concurrent dtmf detection are also supported. this mode supports applications such as digital tam, voice annotation, and recording from and playback to the telephone line. adpcm (4-bit ima) coding is also supported to meet microsoft whql logo requirements. tam mode is supported by three submodes: 1. online voice command mode supports connection to the telephone line or, for s models, a microphone/speaker/handset/headset. 2. voice receive mode supports recording voice or audio data input from the telephone line or, for s models, a microphone/handset/headset. 3. voice transmit mode supports playback of voice or audio data to the telephone line or, for s models, a speaker/handset/headset. voice/speakerphone mode (s models) the s models include additional telephone handset, external microphone, and external speaker interfaces which support voice and full-duplex speakerphone (fdsp) operation. hands-free full-duplex telephone operation is supported in speakerphone mode under host control. speakerphone mode features an advanced proprietary speakerphone algorithm which supports full-duplex voice conversation with acoustic, line, and handset echo cancellation. parameters are constantly adjusted to maintain stability with automatic fallback from full- duplex to pseudo-duplex operation. the speakerphone algorithm allows position independent placement of microphone and speaker. the host can separately control volume, muting, and agc in microphone and speaker channels. 1.3.4 reference design a minipci type iiib data/fax/tam reference design board is available to minimize application design time and costs. the board is pretested to pass fcc part 15, part 68, and ctr 21 for immediate manufacturing. a design package for the board is available in electronic form. the design package includes schematics, bill of materials (bom), vendor parts list (vpl), board layout files in gerber format, and complete documentation. the design can also be used for the basis of a custom design by the oem to accelerate design completion for rapid market entry. 1.4 hardware description smartdaa ? technology (patent pending) eliminates the need for a costly analog transformer, relays, and opto-isolators that are typically used in discrete daa implementations. the programmable smartdaa architecture simplifies product implementation in world-wide markets by eliminating the need for country-specific components. 1.4.1 host side device (hsd) the hsd, packaged in a 100-pin tqfp, includes a pci/minipci/cardbus interface, a modem data pump (mdp), and a smartdaa interface. the pci/minipci/cardbus interface connects directly to an embedded or external pci/minipci/cardbus interface eliminating the need for additional external logic components. the mdp performs telephone line signal modulation/demodulation in a hardware digital signal processor (dsp) which reduces computational load on the host processor. downloadable architecture allows updating of mdp executable code. SMARTHCF mobile modem designers guide 100475a conexant 1-7 conexant proprietary information the smartdaa interface communicates with, and supplies power and clock to, the lsd through the dib. 1.4.2 digital isolation barrier (dib) (oem supplied) the dib electrically dc isolates the hsd from the lsd and telephone line. the hsd is connected to a fixed digital ground and operates with standard cmos logic levels. the lsd is connected to a floating ground and can tolerate high voltage input (compatible with telephone line and typical surge requirements). the dib power and clock transformer (pcxfmr) couples power and clock from the hsd to the lsd. (see mobile product updates for qualified transformers.) the dib data channel supports bidirectional half-duplex serial transfer of data, control, and status information between the hsd and the lsd. 1.4.3 smartdaa line side device (lsd) the lsd includes a line side dib interface (lsdi), a coder/decoder (codec), and a telephone line interface (tli). the lsdi communicates with, and receives power and clock from, the smartdaa interface in the hsd through the dib. lsd power is received from the dib pcxfmr secondary winding through a half-wave rectifying diode and capacitive power filter circuit. the clk input is also accepted from the pcxfmr secondary winding through a capacitor and a resistor in series. information is transferred between the lsd and the hsd through the dib_p and dib_n pins. these pins connect to the hsd dib_datap and dib_datan pins, respectively, through the dib. the tli integrates daa and direct telephone line interface functions and connects directly to the line tip and ring pins, as well as to external line protection components. direct lsd connection to tip and ring allows real-time measurement of telephone line parameters, such as the telephone central office (co) battery voltage, individual telephone line (copper wire) resistance, and allows dynamic regulation of the o ff- hook tip and ring voltage and total current drawn from the central office (co). this allows the modem to maintain compliance with u.s. and world-wide regulations and to actively control the daa power dissipation. 1.4.4 voice codec (vc) (s models) the optional vc, packaged in a 32-pin tqfp, supports voice/full-duplex speakerphone (fdsp) operation with interfaces to a microphone and speaker and to a telephone handset/headset. SMARTHCF mobile modem designers guide 1-8 conexant 100475a conexant proprietary information this page is intentionally blank. SMARTHCF mobile modem designers guide 100475a conexant 2-1 conexant proprietary information 2. technical specifications 2.1 establishing data modem connections dialing dtmf dialing. dtmf dialing using dtmf tone pairs is supported in accordance with itu-t q.23. the transmit tone level complies with bell publication 47001. pulse dialing. pulse dialing is supported in accordance with eia/tia-496-a. blind dialing. the modem can blind dial in the absence of a dial tone if enabled by the x0, x1, or x3 command. modem handshaking protocol if a tone is not detected within the time specified in the s7 register after the last digit is dialed, the modem aborts the cal l attempt. call progress tone detection ringback, equipment busy, and progress tones can be detected in accordance with the applicable standard represented by the country profile currently in affect. answer tone detection answer tone can be detected over the frequency range of 2100 40 hz in itu-t modes and 2225 40 hz in bell modes. ring detection a ring signal can be detected from a ttl-compatible square wave input (frequency is country-dependent). billing protection when the modem goes off-hook to answer an incoming call, both transmission and reception of data are prevented for a period of time determined by country requirement to allow transmission of the billing signal. connection speeds data modem line speed can be selected using the +ms command in accordance with v.25 ter. the +ms command selects modulation, enables/disables automode, and selects transmit and receive minimum and maximum line speeds. automode automode detection can be enabled by the +ms command to allow the modem to connect to a remote modem in accordance with v.25 ter. 2.2 data mode data mode exists when a telephone line connection has been established between modems and all handshaking has been completed. speed buffering (normal mode) speed buffering allows a dte to send data to, and receive data from, a modem at a speed different than the line speed. the modem supports speed buffering at all line speeds. dte-to-modem flow control if the modem-to-line speed is less than the dte-to-modem speed, the modem supports xoff/xon or rts/cts flow control with the dte to ensure data integrity. escape sequence detection the +++ escape sequence can be used to return control to the command mode from the data mode. escape sequence detection is disabled by an s2 register value greater than 127. SMARTHCF mobile modem designers guide 2-2 conexant 100475a conexant proprietary information gstn cleardown (v.90/k56flex, v.34, v.32 bis, v.32) upon receiving gstn cleardown from the remote modem in a non-error correcting mode, the modem cleanly terminates the call. fall forward/fallback (v.90/k56flex, v.34/v.32 bis/v.32) during initial handshake, the modem will fallback to the optimal line connection within k56flex/v.34/v.32 bis/v.32 mode depending upon signal quality if automode is enabled by the +ms command. when connected in v.90/k56flex/v.34/v.32 bis/v.32 mode, the modem will fall forward or fallback to the optimal line speed within the current modulation depending upon signal quality if fall forward/fallback is enabled by the %e1 command. retrain the modem may lose synchronization with the received line signal under poor line conditions. if this occurs, retraining may be initiated to attempt recovery depending on the type of connection. the modem initiates a retrain if line quality becomes unacceptable if enabled by the %e command. the modem continues to retrain until an acceptable connection is achieved, or until 30 seconds elapse resulting in line disconnect. 2.3 error correction and data compression v.42 error correction v.42 supports two methods of error correction: lapm and, as a fallback, mnp 4. the modem provides a detection and negotiation technique for determining and establishing the best method of error correction between two modems. mnp 2-4 error correction mnp 2-4 is a data link protocol that uses error correction algorithms to ensure data integrity. supporting stream mode, the modem sends data frames in varying lengths depending on the amount of time between characters coming from the dte. v.42 bis data compression v.42 bis data compression mode operates when a lapm or mnp connection is established. the v.42 bis data compression employs a string learning algorithm in which a string of characters from the dte is encoded as a fixed length codeword. two dictionaries, dynamically updated during normal operation, are used to store the strings. mnp 5 data compression mnp 5 data compression mode operates during an mnp connection. in mnp 5, the modem increases its throughput by compressing data into tokens before transmitting it to the remote modem, and by decompressing encoded received data before sending it to the dte. 2.4 fax class 1 operation facsimile functions operate in response to fax class 1 commands when +fclass=1 or +fclass=1.0. in the fax mode, the on-line behavior of the modem is different from the data (non-fax) mode. after dialing, modem operation is controlled by fax commands. some at commands are still valid but may operate differently than in data modem mode. calling tone is generated in accordance with t.30. 2.5 voice/tam mode voice and audio functions are supported by the voice mode. voice mode includes three submodes: online voice command mode, voice receive mode, and voice transmit mode. 2.5.1 online voice command mode this mode results from the connection to the telephone line or a voice/audio i/o device (e.g., microphone or speaker) through the use of the +fclass=8 and +vls commands. after mode entry, at commands can be entered without aborting the connection. SMARTHCF mobile modem designers guide 100475a conexant 2-3 conexant proprietary information 2.5.2 voice receive mode this mode is entered when the +vrx command is active in order to record voice or audio data input, typically from a microphone or the telephone line. received analog voice samples are converted to digital form and compressed for reading by the host. at commands control the codec sample rate. received analog mono audio samples are converted to digital form and formatted into 8-bit m -law, a law, linear, or 4-bit ima adpcm format for reading by the host. at commands control the bit length and sampling rate. concurrent dtmf/tone detection is available. 2.5.3 voice transmit mode this mode is entered when the +vtx command is active in order to playback voice or audio data, typically to a speaker or to the telephone line. concurrent dtmf/tone detection is available. digitized audio data is converted to analog form. 2.5.4 speakerphone modes speakerphone modes are selected in voice mode with the following commands: speakerphone on/off (+vsp). this command turns the speakerphone function on (+vsp = 1) or off (+vsp = 0). microphone gain (+vgm= SMARTHCF mobile modem designers guide 2-4 conexant 100475a conexant proprietary information 2.8.2 blacklist parameters the modem can operate in accordance with requirements of individual countries to prevent misuse of the network by limiting repeated calls to the same number when previous call attempts have failed. call failure can be detected for reasons such as no dial tone, number busy, no answer, no ringback detected, voice (rather than modem) detected, and key abort (dial attempt aborted by user). actions resulting from such failures can include specification of minimum inter-call delay, extended delay between calls, and maximum numbers of retries before the number is permanently forbidden ("blacklisted"). up to 20 such numbers may be tabulated. the blacklist parameters are programmable. the current blacklisted and delayed numbers can be queried via at*b and at*d commands, respectively. 2.9 diagnostics 2.9.1 commanded tests diagnostics are performed in response to the &t1 command per v.54. analog loopback (&t1 command). data from the local dte is sent to the modem, which loops the data back to the local dte. last call status report (#ud). this command reports the status of the last call. 2.10 low power sleep mode when not connected in data, fax, or speakerphone mode, the hsd is placed in a low power state. SMARTHCF mobile modem designers guide 100475a conexant 3-1 conexant proprietary information 3. hardware interface 3.1 hsd (p9573) hardware pins and signals 3.1.1 hsd signal interfaces pci bus/minipci/cardbus host interface the host side device conforms to the pci local bus specification version 2.2, minipci specification draft 1.0, and pc card standard for cardbus. it is a memory slave and a bus master for pc host memory accesses (burst transactions). configuration is by pci configuration protocol. the pci bus/minipci/cardbus interface signals are: address and data - 32 bidirectional address/data (ad[31-0]); bidirectional - 4 bus command and byte enable (cbe [3:0]); bidirectional - bidirectional parity (par); bidirectional interface control - cycle frame (frame#); bidirectional - initiator ready (irdy#); bidirectional - target ready (trdy#); bidirectional - stop (stop#); bidirectional - initialization device select (idsel); input - device select (devsel#); bidirectional arbitration - request (req#); output - grant (grant#); input error reporting - parity error (perr#); bidirectional - system error (serr#); bidirectional interrupt - interrupt a (inta#); output system - clock (pciclk); input - reset (pcirst#); input - clock running (clkrun#); input - power management event (pme#), output (-pci model) - status change (stschg#), output (-cb model) power detection and switching vaux enable (vauxen#); output (-pci model) vpci enable (vpcien#); output (-pci model) vpci detect (vpcidet); input vaux detect (vauxdet); input serial eeprom interface a serial eeprom is required to store the device id, vendor id, subsystem id, subsystem vendor id, and power management parameters for the pci configuration space header. the eeprom is also required to store the cis table for cardbus designs. the eeprom must be 2048 (128 x 16) bits or larger for pci bus/minipci applications or 4096 (256 x 16) bits or larger for cardbus applications, and be rated at 1mhz (sromclk is 537.6 khz). for example, the following eeproms or equivalent may be used: microchip 93lc66b (256 x 16), 93lc56b (128 x 16), atmel at93c66 (256 x 16), at93c56 (128 x 16). the eeprom is programmable by the pc via the modem. SMARTHCF mobile modem designers guide 3-2 conexant 100475a conexant proprietary information the eeprom interface signals are: serial data input (sromin); input serial data output (sromout); output clock (sromclk); output chip select (sromcs); output lsd interface (through dib) the dib interface signals are: clock and power positive (pwrclkp); output clock and power negative (pwrclkn); output data positive (dib_datap); input/output data negative (dib_datan); input/output vc interface (s models) the vc interface signals are: modem sleep (iasleep); output master clock (m_clk); output voice serial clock (v_sclk); input voice serial control (v_ctrl); output voice serial frame sync (v_strobe); input voice serial transmit data (v_txsin); output voice serial receive data (v_rxout); input telephone handset interface (s models) the telephone handset interface signals are: voice relay control (voice#); output handset pickup detect (h_pickup); input call progress speaker interface the call progress speaker interface signal is: digital speaker output (dspkout); output dspkout is a square wave output in data/fax mode used for call progress or carrier monitoring. this output can be optionally connected to a low-cost on-board speaker, e.g., a sounducer, or to an analog speaker circuit. 3.1.2 hsd interface signals, pin assignments, and signal definitions the hsd (p9573) 100-pin tqfp hardware interface signals are shown by major interface in figure 3-1, are shown by pin number in figure 3-2 and are listed by pin number in table 3-1. the hsd hardware interface signals are defined in table 3-2. SMARTHCF mobile modem designers guide 100475a conexant 3-3 conexant proprietary information sdxtal1 sdxtal2 clkrun# ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad21 ad22 ad23 ad24 ad25 ad26 ad27 ad28 ad29 ad30 ad31 cbe0# cbe1# cbe2# cbe3# pciclk frame# idsel devsel# irdy# trdy# par req# gnt# inta# stop# perr# serr# pme#/stschg# pcirst# vio vio vauxdet vauxen# vpcien# vpcidet 74 75 86 67 66 65 64 62 61 60 59 56 55 54 53 52 51 50 49 37 35 34 33 32 30 29 28 24 23 21 20 19 17 16 15 57 48 38 25 10 39 27 42 40 41 46 13 12 8 43 44 45 14 9 22 26 80 70 69 71 27pf 5% 28.224 mhz 1m pci bus/ mini pci/ cardbus sromcs sromclk sromin sromout gpio3 gpio4 gpio5 gpio6 spkmute (gpio8) dspkout (gpio11) h_pickup (gpio10) voice# (gpio2) pwrclkp pwrclkn dib_datap dib_datan iasleep dreset# (gpol0) m_clk v_sclk v_strobe v_txsin v_rxout v_ctrl pllvdd pllvss vdd vdd vdd vdd vdd vdd vdd vdd gnd gnd gnd gnd scanen scanmode 76 79 78 77 85 83 82 81 99 87 88 100 92 93 91 90 96 95 5 3 1 4 2 6 97 98 84 7 18 31 47 58 68 94 11 36 63 89 72 73 eeprom md260f3 his p95 100t power detection and switching circuit host side device (hsd) p9573 100-pin tqfp 27pf 5% voice codec ( vc ) 20437 32-pin tqfp sleep por m_clkin m_sck m_strobe m_txsin m_rxout m_cntrlsin +3.3v speaker circuit speaker circuit handset pickup detection circuit voice relay digital isolation barrier (dib) nc nc nc nc 0.1uf 33 +3.3v +3.3v 0 )ljxuh +6' 3 3lq 74)3 +dugzduh ,qwhuidfh 6ljqdov SMARTHCF mobile modem designers guide 3-4 conexant 100475a conexant proprietary information md260f4 po-p95-100tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 v_stro be v_rxout v_sclk v_txsin m _clk v_ctrl vdd inta# pcirst#*/stschg** pciclk gnd gnt# req# pm e# ad31 ad30 ad29 vdd ad28 ad27 ad26 vio ad25 ad24 cbe3# sdxtal2 sdxtal1 scanmode scanen vpcidet vauxen#*/reserved** vpcien#*/reserved** vdd ad0 ad1 ad2 ad3 gnd ad4 ad5 ad6 ad7 vdd cbe0# ad8 ad9 ad10 ad11 ad12 ad13 voice# (gpio 2) spkm ute (gpio8) pllvss pllvdd iasleep dreset# (gpol0) vdd pw rclkn pw rclkp dib_datap dib_datan g nd h_pickup (gpio10) dspkout (gpio11) clkrun# gpio 3 vdd gpio4 gpio5 gpio6 vauxdet srom clk sromin srom out sromcs vio idsel ad23 ad22 ad21 vdd ad20 ad19 ad18 ad17 gnd ad16 cbe2# fram e# irdy# trdy# devsel# stop# perr# serr# par vdd cbe1# ad15 ad14 p9573 * pci bus/mini pci models ** cardbus models )ljxuh +6' 3 3lq 74)3 3lq 6ljqdov SMARTHCF mobile modem designers guide 100475a conexant 3-5 conexant proprietary information 7deoh +6' 3 3lq 74)3 3lq 6ljqdov pin signal label i/o type interface pin signal label i/o type interface 1 v_strobe itpu vc: m_strobe 51 ad13 i/opts pci bus: ad13 2 v_rxout itk vc: m_rxout 52 ad12 i/opts pci bus: ad12 3 v_sclk itpu vc: m_sck 53 ad11 i/opts pci bus: ad11 4 v_txsin ot2 vc: m_txsin 54 ad10 i/opts pci bus: ad10 5 m_clk ot2 vc: m_clkin 55 ad9 i/opts pci bus: ad9 6 v_ctrl ot2 vc: m_cntrlsin 56 ad8 i/opts pci bus: ad8 7 vdd pwr +3.3v 57 cbe0# i/opts pci bus: cbe0# 8 inta# opod pci bus: inta# 58 vdd pwr +3.3v 9 pcirst# ip pci bus: pcirst# 59 ad7 i/opts pci bus: ad7 10 pciclk ip pci bus: pciclk 60 ad6 i/opts pci bus: ad6 11 gnd gnd gnd 61 ad5 i/opts pci bus: ad5 12 gnt# ipts pci bus: gnt# 62 ad4 i/opts pci bus: ad4 13 req# opts pci bus: req# 63 gnd gnd gnd 14 pme#/stschg# opod pci bus: pme# cardbus: stschg# (see note 3) 64 ad3 i/opts pci bus: ad3 15 ad31 i/opts pci bus: ad31 65 ad2 i/opts pci bus: ad2 16 ad30 i/opts pci bus: ad30 66 ad1 i/opts pci bus: ad1 17 ad29 i/opts pci bus: ad29 67 ad0 i/opts pci bus: ad0 18 vdd pwr +3.3v 68 vdd pwr +3.3v 19 ad28 i/opts pci bus: ad28 69 vpcien#/ reserved ot2 pci bus: pwr detection/switching ckt cardbus: reserved (see note 4) 20 ad27 i/opts pci bus: ad27 70 vauxen#/ reserved ot2 pci bus: pwr detection/switching ckt cardbus: reserved (see note 4) 21 ad26 i/opts pci bus: ad26 71 vpcidet itpd pwr detection/switching ckt 22 vio pwr pci bus: vi/o 72 scanen itpd gnd 23 ad25 i/opts pci bus: ad25 73 scanmode itpd gnd 24 ad24 i/opts pci bus: ad24 74 sdxtal1 ix crystal or clock circuit 25 cbe3# i/opts pci bus: cbe3# 75 sdxtal2 ox crystal or nc (if sdxtal1 connected to clock circuit) 26 vio pwr pci bus: vi/o 76 sromcs ot2 srom: chip select (cs) 27 idsel ip pci bus: idsel 77 sromout ot2 srom: data in (di) 28 ad23 i/opts pci bus: ad23 78 sromin itpu srom: data out (do) 29 ad22 i/opts pci bus: ad22 79 sromclk ot2 srom: clock (sk) 30 ad21 i/opts pci bus: ad21 80 vauxdet itpd pwr detection/switching ckt 31 vdd pwr +3.3v 81 gpio6 itpu/ot12 nc 32 ad20 i/opts pci bus: ad20 82 gpio5 itpu/ot12 nc 33 ad19 i/opts pci bus: ad19 83 gpio4 itpu/ot12 nc 34 ad18 i/opts pci bus: ad18 84 vdd pwr +3.3v through 0 w resistor 35 ad17 i/opts pci bus: ad17 85 gpio3 itpu/ot12 nc 36 gnd gnd gnd 86 clkrun# i/opod pci bus: clkrun# 37 ad16 i/opts pci bus: ad16 87 dspkout (gpio11) ot12 ai: digital/analog speaker circuit for call progress 38 cbe2# i/opts pci bus: cbe2# 88 h_pickup (gpio10) itpu line interface: handset pickup detection circuit 39 frame# i/opsts pci bus: frame# 89 gnd gnd gnd 40 irdy# i/opsts pci bus: irdy# 90 dib_datan idd/odd dib: data negative channel 41 trdy# i/opsts pci bus: trdy# 91 dib_datap idd/odd dib: data positive channel 42 devsel# i/opsts pci bus: devsel# 92 pwrclkp odpc dib: pcxfmr primary winding top 43 stop# i/opsts pci bus: stop# 93 pwrclkn odpc dib: pcxfmr primary winding bottom 44 perr# i/opsts pci bus: perr# 94 vdd pwr +3.3v 45 serr# i/opod pci bus: serr# 95 dreset# (gpol0) ot2 vc: por 46 par i/opts pci bus: par 96 iasleep ot2 vc: sleep 47 vdd pwr +3.3v 97 pllvdd pwr +3.3v and to gnd through 0.1 m f 48 cbe1# i/opts pci bus: cbe1# 98 pllvss gnd gnd 49 ad15 i/opts pci bus: ad15 99 spkmute (gpio8) it/ot12 audio circuit: spkr control (output); vaux mode power select (input) 50 ad14 i/opts pci bus: ad14 100 voice# (gpio2) ot12 line interface: voice relay control SMARTHCF mobile modem designers guide 3-6 conexant 100475a conexant proprietary information 7deoh +6' 3 3lq 74)3 3lq 6ljqdov &rqwg notes: 1. i/o types i/opod digital input/output, pci, open drain (pci type = o/d) i/opsts digital input/output, pci, sustained tristate (pci type = s/t/s) i/opts digital input/output, pci, tristate (pci type = t/s) idd input, dib, data channel ip digital input, pci, totem pole (pci type = in) ipts digital input, pci, (pci type = t/s) it digital input, ttl-compatible itk digital input, ttl-compatible, internal keeper itpd digital input, ttl-compatible, internal 75k 25k w pull-down itpu digital input, ttl-compatible, internal 75k 25k w pull-up it/ot2 digital input, ttl-compatible/digital output, ttl-compatible, 2 ma, z internal = 120 w it/ot12 digital input, ttl-compatible/digital output, ttl-compatible, 12 ma, z internal = 32 w ix crystal/clock input odpc output, dib power and clock channel odd output, dib data channel ood digital output, open drain opod digital output, pci, open drain (pci type =o/d) opts digital output, pci, tristate (pci type = t/s) ot2 digital output, ttl-compatible, 2 ma, z internal = 120 w ot12 digital output, ttl-compatible, 12 ma, z internal = 32 w ox crystal output 2. interface legend: nc no internal pin connection dib digital isolation barrier vc voice codec 3. pme#/stschg# pin: pme# supported by p9573-11; stschg# supported by p9573-21. 4. vauxen#/reserved and vpcien#/reserved pins: vauxen# and vpcien# supported by p9573-11; reserved supported by p9573-21. 5. all references to pci bus also apply to minipci and cardbus unless otherwise specified. SMARTHCF mobile modem designers guide 100475a conexant 3-7 conexant proprietary information 7deoh +6' 3 slq 74)3 3lq 6ljqdo 'hilqlwlrqv label pin i/o type signal name/description system sdxtal1 sdxtal2 74 75 ix ox crystal/clock in and crystal out. connect sdxtal1 to a 28.224000 mhz crystal or clock circuit. connect sdxtal2 to the 28.224000 mhz crystal circuit or leave open if sdxtal1 is connected to a clock circuit. (see layout guidelines in section 5.) vdd 7, 18, 31, 47, 58, 68, 94 pwr digital supply voltage. connect to +3.3v. vdd 84 pwr digital supply voltage. connect to +3.3v through a 0 w resistor. note : pin 84 connection to +3.3v through a resistor allows a common board design to be used with either the SMARTHCF p9573 device (pin 84 [vdd] connects to +3.3v through 0 w ) or the smarthsf 11242 device (pin 84 [lp_clk] connects to +3.3v through 240 k w ). gnd 11, 36, 63, 89 gnd digital ground. connect to digital ground. vio 22, 26 pwr i/o signaling voltage reference. connect to pci bus vi/o. used internally for pci clamping. pllvdd 97 pwr digital supply voltage. connect to +3.3v and to gnd through 0.1 m f. pllgnd 98 gnd digital ground. connect to digital ground. scanen 72 itpd scan enable. connect to gnd. scanmode 73 itpd scan mode . connect to gnd. clkrun# 86 i/opod, (o/d) clock running. clkrun# is an input used to determine the status of clk and an open drain output used to request starting or speeding up clk. connect to gnd for pci bus designs. connect to minipci/cardbus clkrun# pin for minipci/cardbus designs. power detection and switching vauxen# 70 ot2 vaux enable. active low output used to enable vaux fet. for use in designs that switch between vaux and vpci for different power states and for retail designs where the target pc may or may not support vaux. (p9573-11 only.) vpcien# 69 ot2 vpci enable. active low output used to enable vpci fet. for use in designs that switch between vaux and vpci for different power states and for retail designs where the target pc may or may not support vaux. (p9573-11 only.) vpcidet 71 itpd vpci detect. the vpcidet input indicates when pci cycles and pcirst# are to be ignored. connect this pin to the pci bus +5v pins for pci bus designs, pci 3.3v for minipci designs, or to cardbus +3.3v pins for cardbus designs. vpcidet is deasserted when the pci bus enters the b3 state. this pin may alternatively be directly driven in embedded designs by using a logical signal, either +5v or +3.3v level, to indicate when the pci bus is in a b3 state. driving this pin low synchronously to the pci clock or when the pci clock is stopped also allows the hsd to be put into a very low power mode. therefore, using this method, if modem operation is not required, modem power consumption can be reduced even while the pci bus is in power state b0. vauxdet 80 itpd vaux detect. active high input used to detect the presence of vaux. connect to pci bus: vaux. at device power on (por), if d3_cold bit in the eeprom is a 1, pmc[15] is set to a 1 if vauxdet is high or pmc[15] is cleared to a 0 if vauxdet is low. serial eeprom interface sromclk 79 ot2 serial rom shift clock. connect to srom sk input (frequency: 537.6 khz). sromcs 76 ot2 serial rom chip select. connect to srom cs input. sromin 78 itpu serial rom device status and data out. connect to srom do output, through 1k w if using a +5v eeprom. sromout 77 ot2 serial rom instruction, address, and data in. connect to srom di input. SMARTHCF mobile modem designers guide 3-8 conexant 100475a conexant proprietary information 7deoh +6' 3 slq 74)3 6ljqdo 'hilqlwlrqv &rqwg label pin i/o type signal name/description pci bus interface pciclk 10 ip (in) pci bus clock. the pciclk (pci bus clk signal) input provides timing for all transactions on pci. connect to pci bus: clk. pcirst# 9 ip (in) pci bus reset. active low input asserted to initialize pci-specific registers, sequencers, and signals to a consistent reset state. connect to pci bus: rst#. ad[31:0] 15-17, 19-21, 23-24, 28-30, 32-35, 37, 49- 56, 59-62, 64- 67 i/opts (t/s) multiplexed address and data. address and data are multiplexed on the same pci pins. connect to pci bus: ad[31-0]. cbe0# cbe1# cbe2# cbe3# 57 48 38 25 i/opts (t/s) bus command and bus enable. bus command and byte enables are multiplexed on the same pci pins. during the address phase of a transaction, cbe[3:0]# define the bus command. during the data phase, cbe[3:0]# are used as byte enables. connect to pci bus: cbe[3:0]#. par 46 i/opts (t/s) parity. parity is even parity across ad[31:00] and cbe[3:0]#. the master drives par for address and write data phases; the bus interface drives par for read data phases. connect to pci bus: par. frame# 39 i/opsts (s/t/s) cycle frame. frame# is driven by the current master to indicate the beginning and duration of an access. connect to pci bus: frame#. irdy# 40 i/opsts (s/t/s) initiator ready. irdy# is used to indicate the initiating agents (bus masters) ability to complete the current data phase of the transaction. irdy# is used in conjunction with trdy#. connect to pci bus: irdy#. trdy# 41 i/opsts (s/t/s) target ready. trdy# is used to indicate s the bus interfaces ability to complete the current data phase of the transaction. trdy# is used in conjunction with irdy#. connect to pci bus: trdy#. stop# 43 i/opsts (s/t/s) stop. stop# is asserted to indicate the bus interface is requesting the master to stop the current transaction. connect to pci bus: stop#. idsel 27 ip (in) initialization device. idsel input is used as a chip select during configuration read and write transactions. connect to pci bus: idsel. devsel# 42 i/opsts (s/t/s) device select. when actively driven, devsel# indicates the driving device has decoded its address as the target of the current access. as an input, devsel# indicates whether any device on the bus has been selected. connect to pci bus: devsel#. req# 13 opts (t/s) reques t. req# is used to indicate to the arbiter that this agent desires use of the bus. connect to pci bus: req#. gnt# 12 ipts (t/s) grant. gnt# is used to indicate to the agent that access to the bus has been granted. connect to pci bus: gnt#. perr# 44 i/opsts (s/t/s) parity error. perr# is used for the reporting of data parity errors. connect to pci bus: perr#. serr# 45 opod (o/d) system error. serr# is an open drain output asserted to report address parity errors, data parity errors on the special cycle command, or any other system error where the result will be catastrophic. connect to pci bus: serr#. inta# 8 opod (o/d) interrupt a. inta# is an open drain output asserted to request an interrupt. connect to pci bus: inta#. pme# 14 opod (o/d) power management event. active low open drain or active high ttl output (selected by the pme drv bit in the eeprom) asserted when a valid ring signal is detected and the pme_en bit of the pmcsr is a 1. this signal should be used only if the target pci bus supports power management wake-up event. connect to the pci bus: pme#. (p9573-11 only.) stschg# 14 opod (o/d) status changed. active low output asserted to alert the host to changes in the rrdy/-bsy bit (prr1) in the pin replacement register (prr) and to the setting of the reqattn bit (esr4) in the extended status register (esr). (p9573-12 only.) SMARTHCF mobile modem designers guide 100475a conexant 3-9 conexant proprietary information 7deoh +6' 3 slq 74)3 6ljqdo 'hilqlwlrqv &rqwg label pin i/o type signal name/description audio interface dspkout (gpio11) 87 ot12 call progress (digital speaker) output. the dspkout digital output reflects the received analog input signal digitized to ttl high or low level by an internal comparator. this signal is used for call progress or carrier monitoring. this output can be optionally connected to a low-cost on-board speaker, e.g., a sounducer, or to an analog speaker circuit. spkmute (gpio8) 99 it/ot12 speaker mute/vaux mode power select. output (typically active low) used to turn off (mute) the speaker during normal operation. applicable to s models only. upon device reset, this pin is temporarily an input and is sampled. if sampled high and vauxdet is high, vpcien# will be asserted when the device is in d0. if sampled low (e.g., spkmute signal is pulled down to gnd through 10k w ) and vauxdet is high, vauxen# will be asserted when the device is in d0. vauxen# is always asserted when vauxdet is high in d3 with pme enabled. either vauxen# or vpcien#, but not both, can be asserted at the same time. telephone line (daa)/audio interface voice# (gpio2) 100 ot12 voice relay control. output (typically active low) used to control the normally open voice relay. the polarity of this output is configurable. h_pickup (gpio10) 88 itpu handset pickup detect. active high input indicating handset pickup. dib interface pwrclkp 92 odpc clock and power positive. provides clock and power to the lsd . connect to dib pcxfmr primary winding top. pwrclkn 93 odpc clock and power negative. provides clock and power to the lsd . connect to dib pcxfmr primary winding bottom. dib_datap 91 idd/odd data positive. transfers data, control, and status information between hsd and lsd . connect to lsd through dib data positive channel components. dib_datan 90 idd/odd data negative. transfers data, control, and status information between hsd and lsd. connect to lsd through dib data negative channel components. gpio interface gpio6 81 itpu/ot12 reserved. gpio5 82 itpu/ot12 reserved. gpio4 83 itpu/ot12 reserved. gpio3 85 itpu/ot12 reserved. SMARTHCF mobile modem designers guide 3-10 conexant 100475a conexant proprietary information 7deoh +6' 3 3lq 74)3 6ljqdo 'hilqlwlrqv &rqwg label pin i/o type signal name/description voice codec (vc) interconnect iasleep 96 ot2 modem sleep. connect to vc sleep pin. dreset# (gpol0) 95 ot2 modem reset. connect to vc por pin. m_clk 5 ot2 master clock output . connect to vc m_clkin pin. v_sclk 3 itpu voice serial clock input. connect to vc m_sck pin. v_strobe 1 itpu voice serial frame sync input. connect to vc m_strobe pin. v_ctrl 6 ot2 voice control output. connect to vc m_cntrlsin pin. v_txsin 4 ot2 voice serial transmit data output. connect to vc m_txsin pin. v_rxout 2 it voice serial receive data input. connect to vc m_rxout pin. notes: 1. i/o types i/opod digital input/output, pci, open drain (pci type = o/d) i/opsts digital input/output, pci, sustained tristate (pci type = s/t/s) i/opts digital input/output, pci, tristate (pci type = t/s) idd input, dib, data channel ip digital input, pci, totem pole (pci type = in) ipts digital input, pci, (pci type = t/s) it digital input, ttl-compatible itpd digital input, ttl-compatible, internal 75k 25k w pull-down itpu digital input, ttl-compatible, internal 75k 25k w pull-up it/ot2 digital input, ttl-compatible/digital output, ttl-compatible, 2 ma, z internal = 120 w it/ot12 digital input, ttl-compatible/digital output, ttl-compatible, 12 ma, z internal = 32 w ix crystal/clock input odpc output, dib power and clock channel odd output, dib data channel ood digital output, open drain opod digital output, pci, open drain (pci type =o/d) opts digital output, pci, tristate (pci type = t/s) ot2 digital output, ttl-compatible, 2 ma, z internal = 120 w ot12 digital output, ttl-compatible, 12 ma, z internal = 32 w ox crystal output 2. interface legend: nc = no internal pin connection reserved = no external connection allowed (may have internal connection). 5. all references to pci bus also apply to minipci and cardbus unless otherwise specified. SMARTHCF mobile modem designers guide 100475a conexant 3-11 conexant proprietary information 3.2 lsd (20463) hardware pins and signals 3.2.1 lsd signal interfaces hsd interface (through dib) the dib interface signals are: clock (clk); input digital power (pwr+); input power digital ground (dgnd); digital ground data positive (dib_p); input data negative (dib_n); input telephone line interface the telephone line interface signals are: ring ac coupled (rac1); input tip ac coupled (tac1); input electronic inductor resistor (eir); output tip and ring dc measurement (trdc); input dac output voltage (dac); output electronic inductor capacitor (eic) electronic inductor output (eio) electronic inductor feedback (eif) resistive divider midpoint (dcf) transmit analog output (txa); output receive analog input (rxi); input receiver gain (rxg); output mov enable (moven); output world-wide impedance 0 (zw0); input us impedance 0 (zus0); input transmit feedback (txf); input transmit output (txo); output 3.2.2 lsd interface signals, pin assignments, and signal definitions the lsd (20463) 32-pin tqfp hardware interface signals are shown by major interface in figure 3-3, are shown by pin number in figure 3-4, and are listed by pin number in table 3-3. the lsd hardware interface signals are defined in table 3-4. SMARTHCF mobile modem designers guide 3-12 conexant 100475a conexant proprietary information rac2 tac2 rac1 tac1 eir eic dac trdc eio eif rxi rxg txa moven (gpio1) zw0 zus0 txo txf dcf vref vc rbias gpio2 10 12 9 11 15 2 6 5 21 22 3 4 18 32 14 17 20 19 16 8 7 13 1 100476_f3-3_his 20463 line side device ( lsd ) 20463 32-pin tqfp electronic inductor, off-hook, pulse dial, and tip and ring vi control agnd_lsd safety and emi protection agnd_lsd ring in filter agnd_lsd 0.1uf 0.1uf 10 uf agnd_lsd echo cancellation and receiver impedance matching and transmitter pulse dial voltage protection (country specific) nc 143k agnd_lsd clk pwr+ avdd dvdd dgnd agnd dib_p dib_n por 27 31 24 26 25 23 28 29 30 gnd_lsd 10uf 0.1uf 1k 1k agnd_lsd digital isolation barrier ( dib ) pwrclkp pwrclkn dib_datap dib_datan data channel power and clock channel 10pf (pcxfmr) 10pf 10 0.1uf 100pf 100pf consult applicable reference desi g n for exact components and values. telephone line connector tip ring 6.2v 10 pf 1k dvdd dvdd nc nc )ljxuh /6' 3lq 74)3 +dugzduh ,qwhuidfh 6ljqdov md245f6 po-20463-32t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 gpio2 eic rxi rxg trdc dac vc vref avdd agnd eif eio txo txf txa zus0 rac1 rac2 tac1 tac2 rbias zw 0 eir dcf m oven (gpio1) pw r+ por dib_n dib_p clk dvdd dgnd 20463 )ljxuh /6' 3lq 74)3 3lq 6ljqdov SMARTHCF mobile modem designers guide 100475a conexant 3-13 conexant proprietary information 7deoh /6' 3lq 74)3 3lq 6ljqdov pin signal label i/o type interface 1 gpio2 it/ot12 nc 2 eic oa telephone line interface components 3 rxi ia telephone line interface components 4 rxg oa telephone line interface components 5 trdc oa telephone line interface components 6 dac oa telephone line interface components 7 vc ref vref through 0.1 f and to agnd_lsd through 0.1 f 8 vref ref vc through 0.1 f and to agnd_lsd through 10 f 9 rac1 ia ring through 1 m w and 0.033 f 10 rac2 ia nc 11 tac1 ia tip through 1 m w and 0.033 f 12 tac2 ia nc 13 rbias ia agnd_lsd through 143 k w 14 zw0 ia telephone line interface components 15 eir ot12 telephone line interface components 16 dcf ia agnd_lsd 17 zus0 ia telephone line interface components 18 txa oa telephone line interface components 19 txf ia telephone line interface components 20 txo oa telephone line interface components 21 eio oa telephone line interface components 22 eif ia telephone line interface components 23 agnd agnd_lsd agnd_lsd 24 avdd pwr lsd dvdd pin 25 dgnd gnd_lsd dib pcxfmr secondary winding bottom through diode and 10 w in series and to gnd_lsd 26 dvdd pwr lsd avdd pin and to gnd_lsd through 10 f and 0.1 f in parallel 27 clk i dib pcxfmr secondary winding bottom through 10 pf and 1 k w in series and through 10 w shared with lsd dgnd pin through diode 28 dib_p i/o dib line side data positive capacitor through 1 k w 29 dib_n i/o dib line side data negative capacitor through 1 k w 30 por it lsd dvdd pin 31 pwr+ pwr dib pcxfmr secondary winding top and to gnd_lsd through 6.2 v zener diode and 0.1 f in parallel 32 moven (gpio1) ot12 telephone line interface components notes: 1. i/o types*: ia analog input it digital input, ttl-compatible oa analog output ot12 digital output, ttl-compatible, 12 ma, z internal = 32 w agnd_lsd isolated lsd analog ground gnd_lsd isolated lsd digital ground 2. interface legend: hsd host side device SMARTHCF mobile modem designers guide 3-14 conexant 100475a conexant proprietary information 7deoh /6' 3lq 74)3 3lq 6ljqdo 'hilqlwlrqv label pin i/o type signal name/description system signals avdd 24 pwr analog power supply. connect to the lsd dvdd pin. see layout guidelines in section 5. agnd 23 agnd_lsd lsd analog ground. lsd analog ground. connect to agnd_lsd at the gnd_lsd/agnd_lsd tie point and to the analog ground plane. see layout guidelines in section 5. por 30 it power-on reset. connect to lsd dvdd pin. vref 8 ref output reference voltage. connect to vc through 0.1 f and to agnd_lsd through 10 f. ensure a very close proximity between this capacitor and the vref pin. vc 7 ref output middle reference voltage. connect to agnd_lsd through 0.1 f. ensure a very close proximity between this capacitor and the vc pin. use a short path and a wide trace to agnd_lsd pin. dib interface signals clk 27 i clock. provides input clock, ac coupled, to the lsd . connect to dib pcxfmr secondary winding bottom through 1 k w and 10 pf in series and through 10 w shared with lsd dgnd pin through diode. pwr+ 31 pwr digital power input . provides input digital power to the lsd. connect to dib pcxfmr secondary winding top, and to gnd_lsd though a 6.2 v zener diode and 0.1 f in parallel. dvdd 26 pwr digital power . connect to pin 24 (avdd) and to gnd_lsd through 10 f and 0.1 f in parallel. dgnd 25 gnd_lsd lsd digital ground. connect to dib pcxfmr secondary winding bottom through diode in series with 10 w , and to gnd_lsd at the gnd_lsd/agnd_lsd tie point. dib_p, dib_n 28, 29 i/o, i/o data and control positive and negative. connect to hsd dib_datap and hsd dib_datan, respectively, each line serially through 1 k w on lsd side and 100 pf in dib. signals are differential, and ping pong between dib and hsd (half duplex). tip and ring interface rac1, tac1 9, 11 ia, ia ring1 ac coupled and tip1 ac coupled. ac coupled voltage from telephone line used to detect ring. connect rac1 to the top of the diode bridge through 1 m w and 0.033 f (200v). connect tac1 to the of the diode bridge through 1 m w and 0.033 f (200v). rac2 tac2 10, 12 ia, ia ring2 ac coupled and tip2 ac coupled. not used. leave open. eir 15 oa electronic inductor resistor. electronic inductor resistor switch. eic 2 oa electronic inductor capacitor switch. internally switched to no connect when pulse dialing and to ground all other times. this is needed to eliminate pulse dial interference from the electronic inductor ac filter capacitor. dac 6 oa dac output voltage. output voltage of the reference dac. trdc 5 ia tip and ring dc measurement. input on-hook voltage (from a resistive divider). used internally to extract tip and ring dc voltage and line polarity reversal (lpr) information. eio 21 oa electronic inductor output. calculated voltage is applied to this output to control offhook, pulse dial, and dc iv mask operation. eif 22 ia electronic inductor feedback. electronic inductor feedback. rxg 4 oa receiver gain. receiver gain output. rxi 3 ia receive analog input. receive signal input. txa 18 oa transmit analog output. transmit signal used for canceling echo in the receive path. moven (gpio1) 32 ot12 mov enable . connect to pulse dial voltage protection circuit for australia/poland/italy use. leave open if not required. rbias 13 ia receiver bias. connect to gnd through 143 k w . dcf 16 ia resistive divider midpoint. connect to lsd analog ground. SMARTHCF mobile modem designers guide 100475a conexant 3-15 conexant proprietary information 7deoh /6' 3lq 74)3 3lq 6ljqdo 'hilqlwlrqv &rqwg label pin i/o type signal name/description tip and ring interface (continued) zw0 14 ia world-wide impedance 0. input signal used to provide line complex impedance matching for world-wide countries. zus0 17 ia us impedance 0. input signal used to provide line impedance matching for u.s. txo 20 oa transmit output. outputs transmit signal and impedance matching signal; connect to transmitter transistor. txf 19 ia transmit feedback. connect to emitter of transmitter transistor. not used gpio2 1 it/ot12 general purpose i/o 2 . leave open if not used. notes: 1. i/o types*: ia analog input it digital input, ttl-compatible oa analog output ot12 digital output, ttl-compatible, 12 ma, z internal = 32 w agnd_lsd isolated lsd analog ground gnd_lsd isolated lsd digital ground *see lsd (20463) digital electrical characteristics (table 3-5) 2. interface legend: hsd host side device 3. interface components may vary (see reference design for exact components and values). 7deoh /6' 'ljlwdo (ohfwulfdo &kdudfwhulvwlfv parameter symbol min. typ. max. units test conditions input voltage low v in -0.30 C 3.60 v vdd = +3.6v input voltage low v il CC1.0v input voltage high v ih 1.6 C C v output voltage low v ol 0 C 0.33 v output voltage high v oh 2.97 C C v input leakage current C -10 C 10 a output leakage current (high impedance) C -10 C 10 a gpio output sink current at 0.4 v maximum C 2.4 C - ma gpio output source current at 2.97 v minimum C 2.4 C - ma gpio rise time/fall time 20 100 ns test conditions unless otherwise noted: 1. test conditions unless otherwise stated: vdd = +3.3 0.3 vdc; ta = 0c to 70c; external load = 50 pf SMARTHCF mobile modem designers guide 3-16 conexant 100475a conexant proprietary information 3.3 vc (20437) hardware pins and signals (s models) microphone and analog speaker interface signals, as well as telephone handset/headset interface signals are provided to support functions such as speakerphone mode, telephone emulation, microphone voice record, speaker voice playback, and call progress monitor. 3.3.1 vc signal interfaces speakerphone interface the following signals are supported: speaker out (m_spkr_out); analog output - should be used in speakerphone designs where sound quality is important microphone (m_mic_in); analog input telephone handset/headset interface the following interface signals are supported: telephone input (m_line_in), input (telin) Coptional connection to a telephone handset interface circuit telephone output (m_line_outp); output (telout) - optional connection to a telephone handset interface circuit center voltage (vc); output reference voltage hsd interface the following interface signals are supported: reset (por); input sleep (sleep); input master clock (m_clkin); input serial clock (m_sck); output control (m_cntrlsin); input serial frame sync (m_strobe); output serial transmit data (m_txsin); input serial receive data (m_rxout); output 3.3.2 vc interface signals, pin assignments, and signal definitions the vc (20437) 32-pin tqfp hardware interface signals are shown by major interface in figure 3-5, are shown by pin number in figure 3-6, and are listed by pin number in table 3-6. the vc (20437) hardware interface signals are defined in table 3-7. SMARTHCF mobile modem designers guide 100475a conexant 3-17 conexant proprietary information md241f7 20437-his voice codec (vc) 20437 32-pin tqfp audio circuit nc spk out mic telin telout host side device (hsd) +3.3v vaa (+3.3v) 1 4 19 21 23 20 22 18 17 25 5 28 26 6 27 iasleep dreset# m_clk v_sclk v_strobe v_txsin v_rxout v_ctrl sleep por m_clkin m_sck m_strobe m_txsin m_rxout m_cntrlsin vdd vdd mavdd vss set3v_bar2 mavss vsub m_dig_speaker m_mic_in m_spkr_out m_line_in m_line_outp m_line_outm vref vc m_mic_bias m_relaya m_relayb m_act90 m_1bit_out d_lpbk_bar nc nc nc 2 13 3 14 9 10 11 12 15 24 16 29 30 31 7 8 32 0.1 agnd 10 0.1 10 nc handset interface nc agnd gnd ferrite ferrite vc_hand )ljxuh 9& 3lq 74)3 +dugzduh ,qwhuidfh 6ljqdov md241f8 po-20437_32t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 sleep m_dig_speaker m_spkr_out por mavdd mavss nc nc m_relaya m_strobe m_rxout m_sck m_txsin m_clkin m_cntrlsin vdd m_line_outp m_line_outm vref vc m_mic_in m_line_in m_mic_bias m_relayb nc d_lpbk_bar m_1bit_out m_act90 vss vsub set3v_bar2 vdd 20437 )ljxuh 9& 3lq 74)3 3lq 6ljqdov SMARTHCF mobile modem designers guide 3-18 conexant 100475a conexant proprietary information 7deoh 9& 3lq 74)3 3lq 6ljqdov pin signal label i/o i/o type interface 1 sleep i itpd hsd: iasleep 2 m_dig_speaker o ot2 nc 3 m_spkr_out o oa speaker interface circuit 4 por i itpu hsd: dreset# 5 mavdd pwr vaa (+3.3v) 6 mavss agnd agnd 7nc nc 8nc nc 9 m_line_outp (telout) o oa handset interface circuit 10 m_line_outm o oa nc 11 vref ref vc through capacitors 12 vc ref agnd through ferrite bead and capacitors and to and to handset interface circuit (vc_hand) through ferrite bead 13 m_mic_in i ia microphone interface circuit 14 m_line_in (telin) i ia handset interface circuit 15 m_mic_bias nc 16 m_relayb nc 17 vdd pwr +3.3v 18 m_cntrlsin i itpd hsd: v_ctrl 19 m_clkin i itpd hsd: m_clk 20 m_txsin i itpd hsd: v_txsin 21 m_sck o ot2 hsd: v_sclk 22 m_rxout o ot2 hsd: v_rxout 23 m_strobe o ot2 hsd: v_strobe 24 m_relaya o ot2od nc 25 vdd pwr +3.3v 26 m_set3v_bar2 i itpu gnd 27 vsub agnd agnd 28 vss gnd gnd 29 m_act90 i itpu nc 30 m_1bit_out o ot2 nc 31 d_lpbk_bar i itpu nc 32 nc nc notes: 1. i/o types: ia analog input it digital input, ttl-compatible itpd digital input, ttl-compatible, internal 75k 25k w pull-down itpu digital input, ttl-compatible, internal 75k 25k w pull-up it/ot2 digital input, ttl-compatible/digital output, ttl-compatible, 2 ma, z internal = 120 w it/ot12 digital input, ttl-compatible/digital output, ttl-compatible, 12 ma, z internal = 32 w oa analog output ot2 digital output, ttl-compatible, 2 ma, z internal = 120 w ot12 digital output, ttl-compatible, 12 ma, z internal = 32 w agnd analog ground gnd digital ground see vc (20437) digital electrical characteristics (table 3-8) and vc (20437) analog electrical characteristics (table 3-9). 2. interface legend: hsd host side device SMARTHCF mobile modem designers guide 100475a conexant 3-19 conexant proprietary information 7deoh 9& 3lq 74)3 3lq 6ljqdo 'hilqlwlrqv label pin i/o type signal name/description system signals vdd 17, 25 pwr digital power supply. connect to +3.3v and digital circuits power supply filter. mavdd 5 pwr analog power supply. connect to +3.3v and analog circuits power supply filter. vss 28 gnd digital ground. connect to gnd. mavss 6 agnd analog ground. connect to agnd. vsub 27 gnd analog ground. connect to agnd. por 4 itpu power-on reset. active low reset input. connect to host reset#. set3v_bar2 26 itpu set +3.3v analog reference. connect to gnd. hsd interconnect sleep 1 itpd ia sleep. active high sleep input. connect to hsd iasleep pin. m_clkin 19 itpd master clock input . connect to hsd m_clk pin. m_sck 21 ot2 serial clock output. connect to hsd v_sclk pin. m_cntrl_sin 18 itpd control input. connect to hsd v_ctrl pin. m_strobe 23 ot2 serial frame sync. connect to hsd v_strobe pin. m_txsin 20 itpd serial transmit data. connect to hsd v_txsin pin. m_rxout 22 ot2 serial receive data. connect to hsd v_rxout pin. telephone line (daa)/audio interface and reference voltage m_line_outp 9 o(df) telephone handset out (telout). single-ended analog data output to the telephone handset circuit. the output can drive a 300 w load. m_line_in 14 i(da) telephone handset out (telin). single-ended analog data input from the telephone handset circuit. m_mic_in 13 i(da) microphone input. single-ended from the microphone circuit. m_spkr_out 3 o(df) modem speaker analog output. the m_spkr_out analog output reflects the received analog input signal. the m_spkr_out on/off and three levels of attenuation are controlled by bits in dsp ram. when the speaker is turned off, the m_spkr_out output is clamped to the voltage at the vc pin. the m_spkr_out output can drive an impedance as low as 300 ohms. in a typical application, the m_spkr_out output is an input to an external lm386 audio power amplifier. vref 11 ref high voltage reference. connect to vc through 10 f and 0.1 f (ceramic) in parallel. ensure a very close proximity between these capacitors and vref pin. vc 12 ref low voltage reference. connect to analog ground through ferrite bead in series with a parallel combination of 10 f and 0.1 f (ceramic). ensure a very close proximity between these capacitors and vc pin. use a short path and a wide trace to agnd pin. also connect to handset interface circuit (vc_hand) through a ferrite bead. SMARTHCF mobile modem designers guide 3-20 conexant 100475a conexant proprietary information 7deoh 9& 3lq 74)3 3lq 6ljqdo 'hilqlwlrqv &rqwg label pin i/o type signal name/description not used m_dig_speaker 2 ot2 not used. leave open. m_line_outm 10 oa not used. leave open. m_relaya 24 ot not used. leave open. m_relayb 16 ot not used. leave open. m_mic_bias 15 oa not used. leave open. m_act90 29 itpu not used. leave open. m_1bit_out 30 ot2 not used. leave open. d_lpbk_bar 31 it not used. leave open. nc 7, 8, 32 nc internal no connect. notes: 1. i/o types: ia analog input it digital input, ttl-compatible itpd digital input, ttl-compatible, internal 75k 25k w pull-down itpu digital input, ttl-compatible, internal 75k 25k w pull-up it/ot2 digital input, ttl-compatible/digital output, ttl-compatible, 2 ma, z internal = 120 w it/ot12 digital input, ttl-compatible/digital output, ttl-compatible, 12 ma, z internal = 32 w oa analog output ot2 digital output, ttl-compatible, 2 ma, z internal = 120 w ot12 digital output, ttl-compatible, 12 ma, z internal = 32 w agnd analog ground gnd digital ground see vc (20437) digital electrical characteristics (table 3-8) and vc (20437) analog electrical characteristics (table 3-9). 2. interface legend: hsd host side device SMARTHCF mobile modem designers guide 100475a conexant 3-21 conexant proprietary information 7deoh 9& 'ljlwdo (ohfwulfdo &kdudfwhulvwlfv parameter symbol min. typ. max. units test conditions input voltage low v in -0.30 C vdd+0.3 v input voltage low v il -0.30 C vdd+0.3 v input voltage high v ih 0.4*vdd C C v output voltage low v ol 0C0.4v output voltage high v oh 0.8*vdd C vdd v input leakage current C -10 C 10 a output leakage current (high impedance) C -10 C 10 a test conditions unless otherwise noted: 1. test conditions unless otherwise stated: vdd = +3.3 0.3 vdc; ta = 0c to 70c; external load = 50 pf 7deoh 9& $qdorj (ohfwulfdo &kdudfwhulvwlfv signal name type characteristic value m_line_in (telin), i (da) input impedance > 70k w m_mic_in ac input voltage range 1.1 vp-p reference voltage +1.35 vdc m_line_outp (telout) o (dd) minimum load 300 w maximum capacitive load 0 f output impedance 10 w ac output voltage range 1.4 vp-p (with reference to ground and a 600 w load) reference voltage +1.35 vdc dc offset voltage 200 mv m_spkr_out o (df) minimum load 300 w maximum capacitive load 0.01 f output impedance 10 w ac output voltage range 1.4 vp-p reference voltage +1.35 vdc dc offset voltage 20 mv test conditions unless otherwise noted: 1. test conditions unless otherwise stated: vdd = +3.3 0.3 vdc; mavdd = +3.3 0.3 vdc, ta = 0c to 70c parameter min typ max units dac to line driver output (600 w load, 3db in scf and ctf) snr/sdr at: 4vp-p differential 2vp-p differential -10dbm differential 88/85 82/95 72/100 db dac to speaker driver output (150 w load, 3db in scf and ctf, -6db in speaker driver) snr/sdr at: 2vp-p 1vp-p -10dbm 88/75 82/80 72/83 db line input to adc (6db in aaf) snr/sdr at C10 dbm 80/95 db input leakage current (analog inputs) -10 10 m a output leakage current (analog outputs) -10 10 m a SMARTHCF mobile modem designers guide 3-22 conexant 100475a conexant proprietary information 3.4 electrical, environmental, and timing specifications 3.4.1 operating conditions and absolute maximum ratings the operating conditions are specified in table 3-10. the absolute maximum ratings are listed in table 3-11. 7deoh 2shudwlqj &rqglwlrqv parameter symbol limits units supply voltage v dd +3.0 to +3.6 vdc operating temperature range t a 0 to +70 c 7deoh $evroxwh 0d[lpxp 5dwlqjv parameter symbol limits units supply voltage v dd -0.5 to +4.0 vdc input voltage v in -0.5 to (vio +0.5)* vdc storage temperature range t stg -55 to +125 c analog inputs v in -0.3 to (mavdd + 0.5) vdc voltage applied to outputs in high impedance (off) state v hz -0.5 to (vio +0.5)* vdc dc input clamp current i ik 20 ma dc output clamp current i ok 20 ma static discharge voltage (25c) v esd 2500 vdc latch-up current (25c) i trig 400 ma * vio = +3.3v 0.3v or +5v 5%. caution: handling cmos devices these devices contain circuitry to protect the inputs against damage due to high static voltages. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltage. an un-terminated input can acquire unpredictable voltages through coupling with stray capacitance and internal cross talk. both power dissipation and device noise immunity degrades. therefore, all inputs should be connected to an appropriate supply voltage. input signals should never exceed the voltage range from 0.5v or more negative than gnd to 0.5v or more positive than vdd. this prevents forward biasing the input protection diodes and possibly entering a latch up mode due to high current transients. 3.4.2 pci bus electrical, switching, and timing characteristics the host bus electrical, switching, and timing characteristics conform to the following specifications: pci local bus specification version 2.2 minipci specification draft 1.0 pc card standard for cardbus SMARTHCF mobile modem designers guide 100475a conexant 3-23 conexant proprietary information 3.4.3 serial eeprom interface timing the serial eeprom interface timing is listed in table 3-12 and is shown in figure 3-7. 7deoh 7lplqj 6huldo ((3520 ,qwhuidfh symbol parameter min typ. max units test condition t css chip select setup 200 (note 1) C C ns t csh chip select hold 500 (note 1) C C ns t dis data input setup 200 (note 1) C C ns t dih data input hold 1600 C C ns t pd0 data input delay 50 C C ns t pd1 data input delay 50 C C ns t df data input disable time C C note 2 ns t sv status valid C C note 3 ns t skh clock high 900 (note 1) C C ns t skl clock low 900 (note 1) C C ns C endurance C 10 6 C cycles notes: 1. minimum times for hsd outputs when pci clock = 33 mhz (times increase with decreasing pci clock frequency). 2. no requirement. 3. timing controlled by software for programming of eeprom. no requirement for eeprom read into hsd. 1219f3-7 wf-eeprom sromcs (cs) sromin (do) (program) sromout (di) sromin (do) (read) sromclk (sk) t css t skl t skh t dih t dis t csh t pd1 t df t df t pd0 t sv )ljxuh :dyhirupv 6huldo ((3520 ,qwhuidfh SMARTHCF mobile modem designers guide 3-24 conexant 100475a conexant proprietary information this page is intentionally blank. SMARTHCF mobile modem designers guide 100475a conexant 4-25 conexant proprietary information 4. crystal specifications recommended surface-mount crystal specifications are listed in table 4-1. recommended through-hole crystal specifications are listed in table 4-2. 7deoh &u\vwdo 6shflilfdwlrqv 6xuidfh 0rxqw characteristic value conexant part no. 5333r02-020 electrical frequency 28.224 mhz nom. frequency tolerance 50 ppm (c l = 16.5 and 19.5 pf) frequency stability vs. temperature 35 ppm (0c to 70c) vs. aging 15 ppm/4 years oscillation mode fundamental calibration mode parallel resonant load capacitance, c l 18 pf nom. shunt capacitance, c o 7 pf max. series resistance, r 1 60 w max. @20 nw drive level drive level 100w correlation; 300w max. operating temperature 0c to 70c storage temperature C40c to 85c mechanical dimensions (l x w x h) 7.5 x 5.2 x 1.3 mm max. mounting smt holder type none suggested suppliers kds america ilsi america vectron technologies, inc. notes characteristics @ 25c unless otherwise noted. supplier information: kds america fountain valley, ca 92626 (714) 557-7833 ilsi america kirkland, wa 98033 (206) 828 - 4886 vectron technologies, inc. lowell, nh 03051 (603) 598-0074 toyocom u.s.a., inc. costa mesa, ca (714) 668-9081 SMARTHCF mobile modem designers guide 4-26 conexant 100475a conexant proprietary information 7deoh &u\vwdo 6shflilfdwlrqv 7kurxjk +roh characteristic value conexant part no. 333r44-011 electrical frequency 28.224 mhz nom. frequency tolerance 50 ppm (c l = 16.5 and 19.5 pf) frequency stability vs. temperature 30 ppm (0c to 70c) vs. aging 20 ppm/5 years oscillation mode fundamental calibration mode parallel resonant load capacitance, c l 18 pf nom. shunt capacitance, c o 7 pf max. series resistance, r 1 35 w max. @20 nw drive level drive level 100w correlation; 500w max. operating temperature 0c to 70c storage temperature C40c to 85c mechanical dimensions (l x w x h) 11.05 x 4.65 x 13.46 mm max. mounting through hole holder type hc-49/u suggested suppliers kds america ilsi america vectron technologies, inc. notes characteristics @ 25c unless otherwise noted. supplier information: kds america fountain valley, ca 92626 (714) 557-7833 ilsi america kirkland, wa 98033 (206) 828 - 4886 vectron technologies, inc. lowell, nh 03051 (603) 598-0074 toyocom u.s.a., inc. costa mesa, ca (714) 668-9081 SMARTHCF mobile modem designers guide 100475a conexant 5-1 conexant proprietary information 5. layout guidelines good engineering practices must be followed when designing a printed circuit board (pcb) containing the modem and voice codec devices. this is especially important for high performance modem operation with high bit rate data and fax and for high quality voice/audio supporting record/play of analog voice and music, and full-duplex speakerphone operation. suppression of noise is essential to the proper operation and performance of the modem, daa, and voice/speakerphone circuits. two major aspects of noise in an oem board design containing the modem device set must be considered: on-board generated noise and off-board generated noise that is coupled on-board can affect analog signal levels (especially low levels) and quality as well as affecting analog-to-digital conversion (adc)/digital-to-analog conversion (dac) operation. of particular concern is noise in frequency ranges affecting modem and audio circuit performance. on-board generated electromagnetic interference (emi) noise that can be radiated or conducted off-board. this noise can affect the operation of surrounding equipment. most local governing agencies have stringent certification requirements that must be met for use in specific environments. in order to minimize the contribution of the circuit design and pcb layout to emi, the designer must understand the major sources of emi and how to reduce emi to acceptable levels. proper pc board layout (component placement and orientation, signal routing, trace thickness and geometry, etc.), component selection (composition, value, and tolerance), interface connections, and shielding are required for the board design to achieve desired modem performance and to obtain emi certification. a board design should also comply with a host interface specification addressing electrical, physical, and environmental requirements. the designer should consult noise suppression techniques described in technical publications and journals, electronics and electrical engineering text books, and component supplier application notes. seminars covering noise suppression techniques are routinely offered by technical and professional associations as well as component suppliers. these guidelines are offered to help achieve good modem performance, minimize audible noise for audio circuit use, and to minimize emi generation. 5.1 emi considerations 5.1.1 general 1. because emi always takes the easiest path to earth ground, ensure that emi has a good planned path to earth ground. a quiet ground is provided by the case (cardbus)/metallic tabs (minipci), not by the ground pins on the bus. (the ground pins provide effective signal returns to the motherboard, however, at high frequencies these traces become inductors that acquire higher impedance with increasing frequency). 2. surround noisy signals, especially clocks, with a wide gnd guard band. pay special attention to where the guard bands are grounded, as the effectiveness of this technique will be greatly diminished with increased physical distance from a good ground point. 3. use multiple vias rather than a single via with power/ground distribution when changing layers on the board. the more vias that are on the board, the lower the impedance. 4. avoid vias on traces carrying high frequency signals. 5. if radiated emissions move 6 or more dbuv just by slightly moving connected cables, the grounding technique used in design should be improved. at this point, maximize dumping emi energy directly to the chassis ground without dumping too much emi energy to scattered ground traces on the board. 6. in a design needing emi filtering, define an additional chassis section adjacent to the case (cardbus)/ tabs (minipci) end of a plug-in card. most emi components (usually ferrite beads/capacitor combinations) can be placed in this section. fill the unused space with a chassis ground plane where possible, and connect it to the case (cardbus)/ tabs (minipci). 7. keep the current paths of separate board functional areas isolated from each other, thereby limiting the propagation of emi to all areas of the board. separate board functional areas include: digital, daa, and analog. 8. place a series terminating resistor as close as possible to the signal source on clock lines or fast edge rate signals. 5.1.2 filtering 1. a general rule of thumb is to filter every connector on the board. on modem/audio boards, these filters take the form of ferrite beads and capacitors. place a ferrite bead in series with the signal and a capacitor between the signal and ground. after the signal is filtered, it must not be exposed to any board noise. therefore, the filter must be as close to the connector as possible and filtered signals kept away from the digital ground and power. SMARTHCF mobile modem designers guide 5-2 conexant 100475a conexant proprietary information 5.1.3 decoupling 1. another way to minimize emi is to short it to ground through proper decoupling capacitors (caps). because traces and component leads become inductors at high frequencies, use surface mount caps if possible, and place them close to the device pin being decoupled. decouple power pins of a device directly to associated ground pins of the device as close to the device as possible - not to a remote ground plane. if you have power and ground planes, connect capacitors to the planes with more than one via. this will decrease the lead inductance and increase the effectiveness of the capacitors. 2. capacitors can reduce emi by shorting high frequencies to ground. this is good if the ground plane is properly grounded (i.e., short path to chassis ground). otherwise, the decoupling caps then need to be used to source as much noise to the ground plane as it can handle. also, note that the desired value of the decoupling cap depends on the frequency to be eliminated. with higher system clock rates it is necessary to have a mixture of values for decoupling caps (e.g., 0.001 uf, 0.01 uf and 0.1 uf). 3. sourcing too much energy to ground can be just as harmful to emi performance as not sourcing enough emi to ground, if the path to ground is poor. the capacitor value chosen for an offending frequency can be mathematically correct but also cause excessive emi ripple on the ground. unless the impedance of ground traces can be reduced, the solution is to reduce the capacitor value. as an example, if the board is excessively radiating at 100 mhz with a 0.01 uf cap, try a 0.047 uf. the idea is to only source as much energy to ground as the ground can handle and no more, or the emi will radiate. capacitor value frequency of reduced emi 0.1 uf 10 mhz 0.01 uf 30 mhz 0.001 uf 100 mhz 4. there is some overlap, as these values will change as inductance of the board comes into effect, and the fact you rarely have just one problem frequency. another rule of thumb, derived from experience, is 0.1 uf for <80 mhz, 0.01 uf for 60- 500 mhz, and 0.001 uf for >400 mhz. the designer should provide several different values for de-coupling capacitors. these should be spread evenly around the power pins of devices on the board. a few capacitors can be placed in open areas of the board to stabilize the power and ground. 5. separate analog power/ground from digital power/ground with inductors or ferrite beads. the side effect of this separation is that the analog circuit cannot dump their high frequency noise to the chassis ground. the emi characteristic of boards can be improved by using adequate decoupling and by limiting the areas of analog power/ground. 6. the de-coupler on the pciclk guard band should be 0.001 uf to handle the clock harmonics. decouple this guard band directly to a vcc pin near the pciclk pin at the pci connector. 5.1.4 optional configurations because fixed requirements of a design may alter emi performance, guidelines that work in one case may deliver little or no performance enhancement in another case. initial board design should, therefore, include flexibility to allow evaluation of optional configurations. these optional configurations may include: 1. chokes in tip and ring lines replaced with jumper wires as a cost reduction if the design has sufficient emi margin. 2. various grounding areas connected by tie points (these tie points can be short jumper wires, solder bridges between close traces, etc.). 3. developing two designs in parallel; one based on a 2-layer board and the other based on a 4-layer board. during the evaluation phase, better performance of one design over another may result in quicker time to market. SMARTHCF mobile modem designers guide 100475a conexant 5-3 conexant proprietary information 5.2 general layout guidelines for a 2-layer pci board follow the guidelines in this section unless otherwise specified by a host bus specification, a local government regulation, or by a specific guideline mentioned in section 5.3. 5.2.1 placing components 1. from the system circuit schematic, identify the digital, analog (for optional voice/speakerphone), and daa circuits and their components, as well as external signal and power connections. note the location of pins for power, ground, digital signals, and analog signals for each device. 2. roughly place digital, daa, and analog sections on the board. a) place the digital section near the host connector. b) place the daa section near the telephone line connector. c) place the analog section near the microphone and speaker connectors, when applicable. 3. place the components starting with the connectors and jacks, then the modem devices (mixed signal devices), and finally the supporting components. keep the digital and analog components and their corresponding traces as separate as possible and confined to their respective sections on the board. a) allow sufficient clearance around connectors and jacks for mating connectors and plugs. b) allow sufficient clearance around components for power and ground traces. c) allow sufficient clearance around sockets to allow the use of component extractors. d) orient components so pins carrying digital signals extend onto the digital portion of each section and pins carrying analog signals extend onto the analog portion section as much as possible. e) place digital components close together in order to minimize signal trace length. 4. place digital section components (see specific layout guidelines). a) place the host side device (hsd) near the pci/minipci/cardbus connector and immediately next to the digital isolation barrier (dib) with digital signal pins toward host interface connector and power, clock and data pins toward the dib. b) place host bus interface components close to the host connector in accordance with the applicable bus interface standard or specification. c) place crystal circuits as close as possible to the hsd. 5. place daa section components (see specific layout guidelines in section 5.3.2). a) place the lsd as close to the dib as possible with analog signal pins toward the telephone line connector and power, clock and data pins toward the dib. b) place the dib interface components between the lsd and the dib. c) place the analog telephone interface components between the lsd and the telephone line connector. 6. place analog section components optional for voice/speakerphone (see specific layout guidelines). a) place the vc with analog signal pins toward the daa section and the microphone and speaker, and digital signals toward the hsd. b) place mixed-signal components to straddle the border between analog and digital sections. c) place the analog components close to and on the side of card containing the analog signals. d) avoid placing noisy components and traces near these analog signal traces. 7. place decoupling (bypass) capacitors close to the pins (usually power and ground) of the device or connector they are decoupling. make the smallest loop area possible between the capacitor and power/ground pins to reduce emi. evenly distribute the decoupling capacitors around the associated device or connector. 8. provide a connector component, usually a zero ohm resistor or a ferrite bead at one point on the pcb to connect one sections ground to another. allow other points for grounds to be connected together if necessary for emi suppression. SMARTHCF mobile modem designers guide 5-4 conexant 100475a conexant proprietary information 5.2.2 power 1. identify digital power (vdd) and analog power (avdd) supply connections. 2. place a 10 f electrolytic or tantalum capacitor in parallel with a ceramic 0.1 f capacitor between power and ground at a few points in the digital section. place one set nearest to where power enters the pcb (edge connector or power connector) and place another set at the furthest distance from where power is supplied to the pcb. these capacitors help to supply current surge demands by the digital circuits and prevent those surges from generating noise on the power lines that may affect other circuits. 3. generally, route all power traces before signal traces. 5.2.3 grounds 1. provide a digital ground plane. a) provide a digital ground plane on the board bottom everywhere except under the daa section and where the analog ground plane is provided. b) connect the digital ground plane to the case (cardbus)/ tabs (minipci) (chassis ground). c) provide digital ground fill, or islands, in unused space in the digital sections on top the board. d) connect digital ground fill to the digital ground plane using multiple vias and to the case/tabs via multiple traces if possible. a) provide digital ground guard bands around critical traces. a) connect digital ground guard bands to the digital ground plane by one or more vias. 2. provide separate and isolated daa digital and daa analog ground planes in the daa section. a) provide a daa analog ground (agnd_lsd) on the board bottom under the daa analog components. b) provide a daa digital ground (gnd_lsd) on the board bottom side under the daa digital components. c) provide daa digital ground fill in unused space around digital components in the daa section on the top the board. ensure that this fill is at least 40 mils from any hot daa signal coming from the telephone line connector. d) connect daa analog ground (lsd_agnd) and daa digital ground (lsd_gnd) together at one point within the daa, i.e., near the lsd agnd (pin 23) and power capacitor. 3. provide an analog ground plane in the analog (voice/speakerphone) section. a) provide analog ground plane on the board bottom under the analog section. b) provide analog ground fill in unused space around analog components in the analog section on top the board. ensure that this fill is at least 40 mils from any hot daa signal coming from the telephone line connector. c) connect the analog and digital ground planes together at a single point, preferably near the case (cardbus)/ tabs (minipci). 5.2.4 trace widths 1. minimize trace width variation on a given trace. 2. provide 25 mil minimum width for power, ground, and critical signal traces. 3. provide 15 mil minimum width for crystal traces. 4. provide 10 mil (preferably 12 - 15 mil) minimum width for analog signal traces (e.g., the m_mic_in, m_line_out, m_line_in, m_spkr_out, vc, and vref). 5. provide 5 mil (preferably 10 mil) minimum width for all other traces. 5.2.5 trace spacing 1. provide 15 to 40 mil minimum spacing between analog and digital ground traces. 2. provide 40 mil minimum spacing around tip and ring signal traces from the telephone line connector to the first resistor, then normal spacing after the resistor. 3. provide 40 mil minimum spacing from br2+ to the first resistor, then normal spacing after the resistor. 4. provide 10 mil minimum spacing for all analog signals. SMARTHCF mobile modem designers guide 100475a conexant 5-5 conexant proprietary information 5. provide 8 mil minimum spacing for all digital signals. 5.2.6 trace routing 1. provide consistent trace routing. emi radiation will occur every time a trace changes impedance, so avoid vias and try to keep a constant trace width for any given signal. 2. keep high-speed digital traces as short as possible. 3. keep sensitive analog traces as short as possible. 4. provide maximum isolation between traces carrying noise sources and noise sensitive inputs. when layout requirements necessitate routing these signals together, separate noise source traces and noise sensitive traces with traces carrying neutral signals. 5. keep digital signals within the digital section and analog signals within the analog section (placement of isolation traces should prevent these traces from straying outside their respective section). 6. route digital traces perpendicular to analog traces to minimize signal cross coupling. 7. provide isolation traces (usually ground traces) to ensure that analog signals are confined to the analog section and digital traces remain out of the analog section. a trace may have to be narrowed to route it though a mixed analog/digital ic, but try to keep the trace continuous. a. route an analog isolation ground trace or fill, at least 50 mil to 100 mil wide, around the border of the analog section; put on both sides of the pcb. b. route a digital isolation ground trace or fill, at least 50 mil to 100 mil wide, and 200 mil wide on one side of the pcb edge, around the border of the digital section. 8. route the traces between components by the shortest possible path. 9. route the traces between bypass capacitors to ic pins, at least 25 mil wide; avoid vias if possible. 10. gather signals that pass between sections (typically low speed control and status signals) together and route them between sections through a path in the isolation ground traces at one (preferred) or two points only. if the path is made on one side only, then the isolation trace can be kept contiguous by briefly passing it to the other side of the pcb to jump over the signal traces. 11. provide rounded or 45 degree corners. avoid right angle (90 degree) turns on high frequency traces. 12. minimize the number of through-hole connections (feedthroughs/vias) on traces carrying high frequency signals. 13. keep all signal traces away from crystal circuits. 14. distribute high frequency signals continuously on a single trace rather than several traces radiating from one point. 15. provide adequate clearance (e.g., 60 mil minimum) around feedthroughs in any internal planes in the daa circuit. 16. eliminate ground loops, which are unexpected current return paths to the power source. SMARTHCF mobile modem designers guide 5-6 conexant 100475a conexant proprietary information 5.3 specific layout guidelines for a 6-layer mini pci board this section describes layout guidelines specifically for a 6-layer data/fax card. components identified in this section refer to a smartdaa-based reference design schematic. for a minipci card, follow design guidelines documented in the minipci specification. 5.3.1 digital section crystal circuit 1. place the two bypass capacitors, the series output resistor and the amplifier feedback resistor as close as possible to the hsd crystal pins to reduce induced noise levels and minimize any parasitic inductance and capacitance which could affect the crystal oscillator (figure 5-2). note: pcb layout of the crystal circuit is extremely critical; undesired parasitics due to poor layout may cause circuit instability preventing proper crystal circuit startup. 2. keep the traces to the hsd crystal pins, sdxtal1 (pin 74) and sdxtal2 (pin 75), extremely short with no bend greater than 45 degrees and containing no vias (figure 5-2). 3. place digital ground fill under the crystal on top the board extending approximately 40 mils beyond the crystal case area. do not put digital ground under the crystal case in the digital ground plane on the bottom of the board. 4. connect the bypass capacitors directly to the digital ground fill. dib interface 1. place and rotate the hsd close to the pci connector and to the dib to minimize trace length of pci and dib signals. 2. place the dib transformer and dib capacitors over the 110-mil (minimum gap = 2.7 mm = 106.3 mil) daa isolation gap with the transformer closest to the hsd such that the pwrclkp, pwrclkn, dib_datap, and dib_datan traces can be routed with no more than one 90 turn rounded at no more than 45 angle, and without vias. note: the pwrclkp and pwrclkn signals generate noise and the trace routing is extremely critical. the pwrclkp and pwrclkn traces must be extremely short, at least 10 mil wide, and be surrounded by gnd guard band. minimize the area used by the pwrclkp and pwrclkn traces. minipci signal routing 1. layout pci traces in accordance with the minipci local bus specification version 1.0. 2. route the pci interface signals directly to the pci connector. the hsd pinouts are arranged such that signals can be routed to the pci connector with only one via if needed. if any signals cross, the net-list is wrong. the essential rules are: consistent trace aperture, minimum number of vias, trace bends at 45 degree angle maximum. 4. provide 15-mil minimum trace width for the pciclk clock signal. keep the trace width as consistent as possible to minimize impedance change. the clocks should always be routed on the top of the board. 5. the minipci specification puts a strict length limit on pci signals. the pciclk trace must be 1.0 0.1" in length. the reference design achieves the required length by performing a zigzag routing with (a) rounded corners for lower emi and (b) approximately double-width traces compared to other pci interface signals for lower impedance/emi (figure 5-1). 6. the pciclk signal is one of the largest sources of emi on pci peripheral designs. surround this trace on both sides by gnd guard bands along the entire length of pciclk. this technique also approximates the required impedance relationship of pciclk with respect to ground distribution. connect this guard band to gnd pins immediately next to the pciclk pin at the pci connector. 5.3.2 daa section note: a daa is governed by local government regulations covering subjects such as component spacing, high voltage suppression, and current limiting. daa isolation gap 1. provide a 110-mil gap (no traces within the gap) around the daa section on the top and bottom of the board with the gap positioned directly under the dib transformer and dib capacitors. SMARTHCF mobile modem designers guide 100475a conexant 5-7 conexant proprietary information daa section grounding 1. provide separate and isolated digital and analog areas in the daa section. 2. provide an isolated daa analog ground plane (lsd_agnd) on the bottom of the board underneath the analog circuits and extending to the 110-mil gap on three sides and to midway underneath the lsd. do not provide a lsd_agnd plane on top of the board due to space restrictions. leave analog components on top separated by gaps. 3. provide an isolated daa digital ground plane (lsd_gnd) on the bottom of the board underneath the digital components and extending to the 110-mil gap on three sides and to midway underneath the lsd. place an lsd_gnd plane on the top of the board, i.e., lsd_gnd islands around components, and extending to the 110-mil gap on three sides and to midway underneath the lsd. connect the top and bottom lsd_gnd planes in several places with vias. 4. connect to lsd_agnd and lsd_gnd planes together at one tie point (u8) near agnd (pin 23) and gnd (dgnd). 5. route separate traces from c28 to avdd (pin 24) and from c28 to dvdd (pin 26) to minimize noise coupling. 6. route a single trace from c28 to c30. 7. route a single trace from c28 to u8 (ground tie) then to agnd (pin 23). 8. all components connections to agnd should be to the agnd_lsd ground plane by a via. dib interface 1. place the lsd within the daa section such that the lsd side with analog signals (pins 9-16) is oriented toward the analog circuits, and the lsd side with digital signals (pins 25-32) is oriented toward the dib. this should allow the dib signals traces to be routed to components and to the lsd without vias. 2. route the dib power and clock signals from the dib to the connecting diode and capacitors and then to the lsd with extremely short traces without vias. try to keep all the components in the path of a straight trace. 3. route the dib data signals from the dib to the connecting resistors and then to the lsd with short traces without vias. dc hold and impedance match interface 1. place the components connecting to rxi (pin 3) extremely close to the rxi pin. 2. place q6 close to txf (pin 19) and txo (pin 20), with txf (pin 19) having priority. 3. provide isolated heat sink planes on the top and bottom of the board for q4 collector. each plane area should be as large as possible (at least the width and twice the length of q4). connect the heat sink planes with no less than nine vias. solder the q4 tab (collector) to the top plane. diode bridge 1. route a 40-mil minimum trace directly from br + to the q4 collector (figure 5-4). 2. route a 14-mil trace from thick trace to r6, c10 and c12 (figure 5-4). 3. provide 40-mil spacing around the trace from br2+ to the first resistor, then normal spacing after the resistor. 4. connect the mov between br2+ and br2- vc and vref circuit 5. place c42 extremely close to vref (pin 8) and vc (pin 7) and place c44 immediately next to c42. 6. route a single extremely short trace from c42 to vref (pin 8). 7. route a single, short, straight trace from vc (pin 7) to the common nodes of c42 and c44. 8. route an extremely short trace from c44 to a via connected to agnd_lsd. telephone line interface 9. connect the 1000 pf 2 kv capacitor to telephone line tip to chassis gnd across the 110-mil gap immediately next to the rj-11 plug. 10. connect the 1000 pf 2 kv capacitor to telephone line ring to chassis gnd across the 110-mil gap immediately next to the rj-11 plug. 11. provide 25-30 mil traces for the tip and ring traces. SMARTHCF mobile modem designers guide 5-8 conexant 100475a conexant proprietary information 12. provide 40-mil spacing around traces from tip and ring at the rj-11 plug to br2 and the first resistor, then normal spacing after the resistor. 13. provide 10 mil spacing minimum for other analog signal traces. 14. minimize the number of signal traces on the bottom of the board. handset interface (optional) 1. connect the 1000 pf 2 kv capacitor to handset tip to chassis gnd across the 110-mil gap immediately next to the rj- 11 plug. 2. connect the 1000 pf 2 kv capacitor to handset ring to chassis gnd across the 110-mil gap immediately next to the rj-11 plug. 3. position the voice relay and handset pickup detector with the daa section. SMARTHCF mobile modem designers guide 100475a conexant 5-9 conexant proprietary information 3&,&/. wudfh ohqjwk vxuurxqghg e\ d jxdug edqg ri '*1' grxeoh wudfh dshuwxuh 0lqlpl]h qxpehu ri yldv ghjuhh dqjoh frqvlvwhqw wudfh dshuwxuh )ljxuh 3&,&/. *xdug %dqg 7hfkqltxh crystal capacitor capacitor good ground plane connection good ground plane connection minimum trace lengths feeback resistor minimum trace lengths )ljxuh &u\vwdo 6roxwlrq SMARTHCF mobile modem designers guide 5-10 conexant 100475a conexant proprietary information 3rzhu dqg jurxqg glvwulexwlrq qhwzrun yld wklfn wudfhv frsshu srxulqj wh fkqltxh zk huhyhu shuplvvleoh )ljxuh 3rzhu dqg *urxqg 'lvwulexwlrq br2 - + ac ac q4 b c e r6 c10 c12 locations for r6, c10 & c12 may vary by design )ljxuh %ulgjh &rqqhfwlrqv SMARTHCF mobile modem designers guide 100475a conexant 5-11 conexant proprietary information 5.4 package dimensions the 100-pin tqfp package dimensions are shown in figure 5-5. the 32-pin tqfp package dimensions are shown in figure 5-6. detail a coplanarity = 0.08 max. 0.60 +0.15, -0.10 0.14 .03 16.00 0.15 16.00 0.15 14.00 0.05 12.00 ref 12.00 ref 14.00 0.05 pin 1 ref 13.87 0.05 14.00 0.05 1.00 ref 1.00 .05 0.50 ref 13.87 0.05 14.00 0.05 0.500 bsc 0.22 0.05 ref. 100-pin tqfp (gp00-d530) pd-tqfp-100-d530 (032699) detail a 0.10 .05 )ljxuh 3dfndjh 'lphqvlrqv 3lq 74)3 SMARTHCF mobile modem designers guide 5-12 conexant 100475a conexant proprietary information detail a a1 l1 c l a d1 a2 millimeters 0.05 8.75 0.5 0.30 0.13 1.6 max 0.15 1.4 ref 9.25 7.0 ref 5.6 ref 0.75 1.0 ref 0.80 bsc 0.40 0.19 0.10 max 0.0020 0.3445 0.0197 0.0118 0.0051 a a1 a2 d d1 d2 l l1 e b c coplanarity min. max. min. max. inches* dim. ref: 32-pin tqfp (gp00-d262) * metric values (millimeters) should be used for pcb layout. english values (inches) are converted from metric values and may include round-off errors. 0.0630 max 0.0059 0.0551 ref 0.3642 0.2756 ref 0.2205 ref 0.0295 0.0394 ref 0.0315 bsc 0.0157 0.0075 0.004 max pd-tqfp-32 (040395) detail a d1 e b d d2 d1 d1 d d2 pin 1 ref )ljxuh 3dfndjh 'lphqvlrqv slq 74)3 SMARTHCF mobile modem designers guide 100475a conexant 6-1 conexant proprietary information 6. host software interface 6.1 pci configuration registers the pci configuration registers are located in the hsd. table 6-1 identifies the configuration register contents that are supported in the hsd: 7deoh 3&, &rqiljxudwlrq 5hjlvwhuv bit offset (hex) 31:24 23:16 15:8 7:0 00 device id vendor id 04 status (see table 6-2) command (see table 6-3) 08 class code revision id 0c not implemented header type latency timer not implemented 10 base address 0 - memory (hsd) 14 base address 1 C i/o (dummy) 18 unused base address register 1c unused base address register 20 unused base address register 24 unused base address register 28 cis pointer (cardbus only) 2c subsystem id subsystem ve ndor id 30 not implemented 34 reserved cap ptr 38 reserved 3c max latency min grant interrupt pin interrupt line 40 power management capabilities (pmc) (see table 6-4) next item ptr = 0 capability id =01h 44 data pmcsr_bse = 0 bridge support extensions power management control/status register (pmcsr) (see table 6-5) SMARTHCF mobile modem designers guide 6-2 conexant 100475a conexant proprietary information 6.1.1 0x00 - vendor id field this 16-bit read-only field identifying the device manufacturer is loaded from the serial eeprom after reset events. the value is 14f1 for conexant. 6.1.2 0x02 - device id field this 16-bit read-only field identifying the particular device is loaded from the serial eeprom after reset events. the default device id if serial eeprom is not loaded is 0x1085. 6.1.3 0x04 - command register command register 15 C 10 9 8 7 6 5 4 3 2 1 0 reserved r/w r/w 0 r/w 0 0 0 r/w r/w r/w r/w indicates the bit is read or write. the command register bits are described in table 6-2. 7deoh &rppdqg 5hjlvwhu bit description 0 controls a devices response to i/o space accesses. a value of 0 disables the device response. a value of 1 allows the device to respond to i/o space accesses. the bit state is 0 after pcirst# is deasserted. 1 controls a devices response to memory space accesses. a value of 0 disables the device response. a value of 1 allows the device to respond to memory space accesses. the bit state is 0 after pcirst# is deasserted. 2 controls a devices ability to act as a master on the pci bus. a value of 0 disables the device from generating pci accesses. a value of 1 allows the device to behave as a bus master. the bit state is 0 after pcirst# is deasserted. 5-3 not implemented. 6 this bit controls the devices response to parity errors. when the bit is set, the device must take its normal action when a parity error is detected. when the bit is 0, the device must ignore any parity errors that it detects and continue normal operation. the bit state is 0 after pcirst# is deasserted. 7 this bit is used to control whether or not a device does address/data stepping. this bit is read only from the pci interface. it is loaded from the serial eerom after pcirst# is deasserted. 8 this bit is an enable bit for the serr# driver. a value of 0 disables the serr# driver. a value of 1 enables the serr# driver. the bit state is 0 after pcirst# is deasserted. 9 this bit controls whether or not a master can do fast back-to-back transactions to different devices. a value of 1 means the master is allowed to generate fast back-to-back transactions to different agents as described in section 3.4.2 of the pci 2.1 specification. a value of 0 means fast back-to-back transactions are only allowed to the same agent. the bit state is 0 after pcirst# is deasserted. 15-10 reserved SMARTHCF mobile modem designers guide 100475a conexant 6-3 conexant proprietary information 6.1.4 0x06 - status register status register bits 15 14 13 12 11 10 C 9 8 7 6 5 4 3 - 0 r/c r/c r/c r/c r/c 01 r/c 0 0 0 1 0000 r/c indicates the bit is readable and clearable (by writing a 1 to corresponding bit position) the status register bits are described in table 6-3. status register bits may be cleared by writing a 1 in the bit position corresponding to the bit position to be cleared. it is not possible to set a status register bit by writing from the pci bus. writing a 0 has no effect in any bit position. 7deoh 6wdwxv 5hjlvwhu bit description 3-0 reserved 4 extended capabilities = 1. 7-5 not implemented. 8 this bit is only implemented by bus masters. it is set when three conditions are met: 1) the bus agent asserted perr# itself or observed perr# asserted; 2) the agent setting the bit acted as the bus master for the operation in which the error occurred; and 3) the parity error response bit (command register) is set. 10-9 these bits encode the timing of devsel#. 01 is supported corresponding to medium speed. 11 signaled target abort. not implemented. 12 received target abort. this bit must be set by a master device whenever its transaction is terminated with target-abort. 13 received master abort. this bit must be set by a master device whenever its transaction (except for special cycle) is terminated with master-abort. 14 signaled system error. this bit must be set whenever the device asserts serr#. 15 detected parity error. this bit must be set by the device whenever it detects a parity error, even if parity error handling is disabled (as controlled by bit 6 in the command register). 6.1.5 0x08 - revision id field this 8-bit read-only field identifying the device revision number is hardcoded in the device. 6.1.6 0x09 - class code field this 24-bit field, contains three 8-bit sub-fields. the upper byte is a base class code: 07 indicates a communications controller. the middle byte is a sub-class code: 80 indicates other type of device. the lower byte is 00 which indicates no register level programming defined. the value of the entire class code field is 0x078000. 6.1.7 0x0d - latency timer register the latency timer register specifies, in units of pci bus clocks, the value of the latency timer for this pci bus master. this register has 5 read/write bits (msbs) plus 3 bits of hardwired zero (lsbs). the latency timer register is loaded into the pci latency counter each time frame# is asserted to determine how long the master is allowed to retain control of the pci bus. this register is loaded by system software. the default value for latency timer is 00. 6.1.8 0x0e - header type field hardwired to 00. 6.1.9 0x28 - cis pointer register this register points to the cis memory located in the hsds memory space. SMARTHCF mobile modem designers guide 6-4 conexant 100475a conexant proprietary information 6.1.10 0x2c - subsystem vendor id register subsystem vendor id register is supported. loaded from the serial eeprom after pcirst# is deasserted. 6.1.11 0x2e- subsystem id register subsystem id register is supported. loaded from the serial eeprom after pcirst# is deasserted. 6.1.12 0x34 - cap ptr capabilities pointer (cap_ptr) at offset 0x34 containing hardcoded value 0x40. 6.1.13 0x3c - interrupt line register the interrupt line register is a read/write 8-bit register. post software will write the value of this register as it initializ es and configures the system. the value in this register indicates which of the system interrupt controllers the devices interrupt pi n is connected to. 6.1.14 0x3d - interrupt pin register the interrupt pin register tells which interrupt pin the device uses. the value of this register is 0x01, indicating that inta# will be used. 6.1.15 0x3e - min grant register the min grant register is used to specify the devices desired settings for latency timer values. the value specifies a period of time in units of 0.25 microsecond. min grant is used for specifying the desired burst period assuming a 33 mhz clock. this register is loaded from the serial eeprom after pcirst# is deasserted. 6.1.16 0x3f - max latency register the max latency register is used to specify the devices desired settings for latency timer values. the value specifies a period of time in units of 0.25 microsecond. min latency specifies how often the device needs to gain access to the pci bus. this register is loaded from the serial eeprom after pcirst# is deasserted. 6.1.17 0x40 - capability identifier the capability identifier is set to 01h to indicate that the data structure currently being pointed to is the pci power management data structure. 6.1.18 0x41 - next item pointer the next item pointer register describes the location of the next item in the functions capability list. the value given is an offset into the functions pci configuration space. the value of 00h indicates there are no additional items in the capabilitie s list. SMARTHCF mobile modem designers guide 100475a conexant 6-5 conexant proprietary information 6.1.19 0x42 - pmc - power management capabilities the hsd contains power management as described in the pci power management specification, revision 1.0 draft, dated mar 18, 1997. the hsd configuration registers include the following power management features: status register bit 4 set to 1 to indicate support for new capabilities capabilities pointer (cap_ptr) at offset 0x34 containing hardcoded value 0x40 power management register block at offset 0x40 and 0x44 (see table 6-1) the power management capabilities register is a 16-bit read-only register which provides information on the capabilities of the function related to power management (table 6-4). 7deoh 3rzhu 0dqdjhphqw &dsdelolwlhv 30& 5hjlvwhu bit r/w description 2:0 r version. 010b indicates compliance with revision 1.0 of the pci power management interface specification. 3 r pme clock. hard coded to 0 to indicate that the pci clock is not required for pme generation. 4 r reserved (= 0). 5 r dsi (device specific initialization). loaded from serial eeprom. 8:6 r aux. current. loaded from serial eeprom. 9 r d1_support. when set to a 1, the hsd device supports d1 power state (loaded from serial eeprom). 10 r d2_ support. when set to a 1, the hsd device supports d2 power state (loaded from serial eeprom). 15:11 r these 5 bits indicate which power states allow assertion of pme (loaded from serial eeprom). a value of 0 for any bit indicates that the function cannot assert the pme# signal while in that power state. bit 11: 1 = pme# can be asserted from d0 bit 12: 1 = pme# can be asserted from d1 bit 13: 1 = pme# can be asserted from d2 bit 14: 1 = pme# can be asserted from d3hot bit 15: 1 = pme# can be asserted from d3cold. 6.1.20 0x44 - pmcsr - power management control/status register (offset = 4) this 16-bit register is used to manage the pci functions power management state as well as to enable/monitor power management events (table 6-5). 7deoh 3rzhu 0dqdjhphqw &rqwuro6wdwxv 5hjlvwhu 30&65 bit r/w description 1:0 r/w power state. 00 = d0 01 = d1 10 = d2 11 = d3. 7:2 r reserved (= 000000b). 8 r/w pme_en. a 1 enables pme assertion. 12:9 r/w data_select. selects data and data scale fields. 14:13 r data scale. associated with data field. loaded from serial eeprom. 15:11 r/c pme_status. this bit is sticky w hen pme assertion from d3_cold is supported. pme_status = 1 indicates pme asserted by the hsd device. writing 1 clears pme_status. writing 0 has no effect. r: bit(s) is (are) read only. r/w: bit(s) is (are) readable and writeable. r/c: bit(s) is (are) readable, and clearable by writing 1 (bit may not be set by writing). SMARTHCF mobile modem designers guide 6-6 conexant 100475a conexant proprietary information 6.1.21 0x46 - pmcsr_bse - pmcsr pci to pci bridge support extensions pmcsr_bse is cleared to 0 to indicate that bus power/clock control policies have been disabled. 6.1.22 0x47 - data this register is used to report the state dependent data requested by the data_select field. the value of this register is scal ed by the value reported by the data_scale field. 6.2 base address register hsd provides a single base address register. the base address register is a 32 bit register that is used to access the hsd register set. bits 3:0 are hard-wired to 0 to indicate memory space. bits 15-4 will be hard-wired to 0. the remaining bits (31 - 16) will be read/write. this specifies that this device requires a 64k byte address space. after reset, the base address register contains 0x00000000. the 64k byte address space used by the hsd is divided into 4k-byte regions. each 4k-byte region is used as table 6-6. 7deoh +6' $gguhvv 0ds address [15:12] address [11:0] region name description 0x0 0x0-0xfff basic2 registers buffers, control, and status registers 0x1 0x0-0xfff cis memory data loaded from serial eeprom for card bus applications 0x2 0x0-0xfff dsp scratch pad access to dsp scratch pad registers 0x3 0x0-0xfff reserved 0x4 0x0-0xfff reserved 0x5-0xf 0x0-0xfff reserved. SMARTHCF mobile modem designers guide 100475a conexant 6-7 conexant proprietary information 6.3 serial eeprom interface the pci configuration space header and power management registers customizable fields are loaded from eeprom during power on reset and during d3 to d0 power transition soft reset. if the eeprom is missing, default hard-coded values are used. this section describes how the eeprom content maps into the registers. the pci configuration space header and power management information is used by the pc bios/windows os to find the driver for this board and also to find out the extent pci power management is typically supported on the modem board. obtain the appropriate eeprom.txt file (unique to each software configuration) from the local conexant sales office. 6.3.1 supported eeprom sizes two eeprom sizes are supported: 256 by 16 bit (e.g., 93lc66b) as shown in table 6-7 and 128 by 16 bit (e.g., 93lc56b) as shown in table 6-8. the difference is the 256-word version supports modem default country selection from the eeprom and also supports cardbus designs, whereas the 128-word version supports neither. the eeprom text file used by the dos4gw b2eprom program utility lists the eeprom content 8 bits per line in hexadecimal format. the least significant 8 bits are listed first followed by the most significant 8 bits of the 16-bit word. 7deoh ((3520 &rqwhqw iru :rugv e\ %lwv shu :rug address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 device id 01 vendor id 02 subsystem device id 03 subsystem vendor id 04 max_lat min_gnt 05 dont care pmc bit 8 pmc bit 7 pmc bit 6 pme drv class code 06 sub-class code prog. i/f 07 cardbus cis pointer high 08 cardbus cis pointer low 09 d0c d1c d2c d3c d0d d1d d2d d3d 0a d3 power consumed d2 power consumed 0b d1 power consumed d0 power consumed 0c d3 power dissipated d2 power dissipated 0d d1 power dissipated d0 power dissipated 0e d3_ cold d3_ hot d2 d1 d0 d2_ state d1_ state dsi load cisram count 0f-fe dont care dont care ff dont care dont care 7deoh ((3520 &rqwhqw iru :rugv e\ %lwv shu :rug address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 device id 01 vendor id 02 subsystem device id 03 subsystem vendor id 04 max_lat min_gnt 05 dont care pmc bit 8 pmc bit 7 pmc bit 6 pme drv class code 06 sub-class code prog. i/f 07 cardbus cis pointer high 08 cardbus cis pointer low 09 d0c d1c d2c d3c d0d d1d d2d d3d 0a d3 power consumed d2 power consumed 0b d1 power consumed d0 power consumed 0c d3 power dissipated d2 power dissipated 0d d1 power dissipated d0 power dissipated 0e d3_ cold d3_ hot d2 d1 d0 d2_ state d1_ state dsi load cisram count 0f-7f dont care dont care SMARTHCF mobile modem designers guide 6-8 conexant 100475a conexant proprietary information 6.3.2 definitions device id register this mandatory 16-bit register identifies the type of device and is assigned by conexant. valid values are: modem-interface modem part number device id comments SMARTHCF/m-pci p9573-11 + 20463-12 1463 data/fax SMARTHCF/m-pci p9573-11 + 20463-12 1464 data/fax/remote tam SMARTHCF/ms-pci p9573-11 + 20463-12 + 20437-11 1465 data/fax/voice/speakerphone SMARTHCF/ms-pci p9573-11 + 20463-12 + 20437-11 1466 full-featured minus handset SMARTHCF/mw-pci p9573-11 + 20463-11 1453 data/fax SMARTHCF/mw-pci p9573-11 + 20463-11 1454 data/fax/remote tam SMARTHCF/mws-pci p9573-11 + 20463-11 + 20437-11 1455 data/fax/voice/speakerphone SMARTHCF/mws-pci p9573-11 + 20463-11 + 20437-11 1456 full-featured minus handset SMARTHCF/m-cb p9573-21 + 20463-12 1363 data/fax SMARTHCF/m-cb p9573-21 + 20463-12 1364 data/fax/remote tam SMARTHCF/ms-cb p9573-21 + 20463-12 + 20437-11 1365 data/fax/voice/speakerphone SMARTHCF/ms-cb p9573-21 + 20463-12 + 20437-11 1366 full-featured minus handset SMARTHCF/mw-cb p9573-21 + 20463-11 1353 data/fax SMARTHCF/mw-cb p9573-21 + 20463-11 1354 data/fax/remote tam SMARTHCF/mws-cb p9573-21 + 20463-11 + 20437-11 1355 data/fax/voice/speakerphone SMARTHCF/mws-cb p9573-21 + 20463-11 + 20437-11 1356 full-featured minus handset vendor id register this mandatory 16-bit register identifies the manufacturer of the device. the value in this read-only register is assigned by a central authority (i.e., the pci sig) that controls the issuance of the numbers. the value is 14f1 for conexant. subsystem vendor id and subsystem device register the subsystem vendor id is obtained from the sig, while the vendor supplies its own subsystem device id. these values are supplied by oem. until these values are assigned, conexant uses default values for subsystem vendor id and subsystem device id which are the same as vendor id and device id, respectively. a pci functional device may be contained on a card or be embedded within a subsystem. two cards or subsystems that use the same pci functional device core logic would have the same vendor and device ids. these two optional registers are used to uniquely identify the add-in card or subsystem that the functional device resides within. software can then distinguish the difference between cards or subsystems manufactured by different vendors but with the same pci functional device on the card or subsystem. a value of zero in these registers indicates that there isnt a subsystem vendor and subsystem id associated with the device. min_gnt register this register is assigned by conexant. the value is 00. this register is optional for a bus master and not applicable to non-master devices. this register indicates how long the master would like to retain pci bus ownership whenever it initiates a transaction. the value hardwired into this register indicates how long a burst period the device needs (in increments of 250 ns). a value of zero indicates the device has no stringent requirements in this area. this information is useful in programming the algorithm to be used in the pci bus arbiter (if it is programmable). SMARTHCF mobile modem designers guide 100475a conexant 6-9 conexant proprietary information max_lat register this register is assigned by conexant. the value is 00. this register is optional for a bus master and not applicable to non-master devices. the specification states that this read-on ly register specifies how often the device needs access to the pci bus (in increments of 250 ns). a value of zero indicates the device has no stringent requirements for the data. this register could be used to determine the priority-level the bus arbiter assigns to the master. pmc [8:6] and pme drv type these fields are assigned by conexant. pmc [8:6]: this 3- bit field reports the 3.3vaux auxiliary current requirements for the pci function. if the data register has been implemented by this function then 1) reads of this field must return a value of 000b 2) data register takes precedence over this field for 3.3vaux current requirements. if pme# generation from d3cold is not supported by the function (pmc(15)=0), then this field must return a value of 000b when read. the value is 000b. pme drv type: this bit sets the driving capability of the pme pin (0 = active high ttl, 1 = active low open drain). the value is 1. class code register (class code, sub-class code, prog. i/f) this register is always mandatory and is assigned by conexant. the value is 07 for class code, 80 for sub-class code, and 00 for prog. i/f. this register is a 24-bit read-only register divided into three sub-registers: base class, sub-class, and prog. i/f (programmin g interface). the register identifies the basic function of the device via the base class (i.e. for modems: simple communications controller), a more specific device sub-class (i.e. for modems: other communications device), and in some cases a register- specific programming interface (not used for modems). cardbus cis pointer (cardbus cis pointer high, cardbus cis pointer low) this register is optional and is assigned by conexant. the value is 00000000. this optional register is implemented by devices that share silicon between cardbus and pci. this field points to the card information structure, or cis, for the cardbus card. this register is read-only and contains the offset of the cis. data scale pmcsr[14:13] (d0c, d1c, d2c, d3c, d0d, d1d, d2d, d3d) this value is supplied by the oem since conexant implements the data register. until these values are assigned, conexant uses a default value 0000. this field is required for any function that implements the data register. the data scale is a 2- bit read-only field which indicates the scaling factor to be used when interpreting the value of the data register. the value and meaning of this field will vary depending on which data value has been selected by the data_select field (pmcsr[12:09]). there are 4 data scales to select 1) 0 = unknown 2) 1 = 0.1x, 3) 2 = 0.01x, 4) 3 = 0.001x where x is defined by the data select field. data register (d3, d2, d1, d0 power consumed and d3, d2, d1, d0 power dissipated) this value is supplied by the oem since conexant implements the data register. until these values are assigned, conexant uses a default value of 0000000000000000. the data register is an optional, 8-bit read-only register that provides a mechanism for the function to report state dependent operating data such as power consumed or heat dissipation. typically the data returned through the data register is a static copy (look up table, for example) of the functions worst case dc characteristics data sheet. this data, when made available to system software could then be used to intelligently make decisions about power budgeting, cooling requirements, etc. the data returned by the data register is selected by the data select field (pmcsr[12:09]). load cisram count (cis _size) this register is optional and is assigned by conexant. the value is 00. this register contains an 8-bit value indicating the number of double words to be loaded into the cisram for cardbus support. SMARTHCF mobile modem designers guide 6-10 conexant 100475a conexant proprietary information pmc[15:9, 5] (d3_cold, d3_hot, d2, d1, d0, d2_support, d1_support, dsi) pmc[15:11]: pme_support (d3_cold, d3_hot, d2, d1, d0)- this 5-bit field indicates the power states in which the function may assert pme#. a value of 0b for any bit indicates that the function is not capable of asserting the pme# signal while in tha t power state. d2 and d1 must be 0 since the modem does not support these states. the rest of the values are supplied by the oem and the values depend upon the systems in which the modem will be installed. conexant uses a default value of 49. this is for a system which does not support d3cold but supports d3hot. when d3_cold is a 1, pmc[15] is set to a 1 if vauxdet is high at device power on reset (por) or is reset to a 0 if vauxdet is low at por. when d3_cold is a 0, pmc[15] is always 0, regardless of the vauxdet level. pmc[10] (d2_support): if this bit is a 1 then function supports the d2 power management state. currently the modems do not support this state and therefore this field must be 0. pmc[9] (d1_support): if this bit is a 1 then function supports the d1 power management state. currently the modems do not support this state and therefore this field must be 0. dsi: the device specific initialization bit indicates whether special initialization of this function is required (beyond the standard pci configuration header) before the generic class device driver is able to use it. this bit should always be set to 1. note: for more information, refer to pci bus power management interface specification. notes (inside back cover) further information literature@conexant.com 1-800-854-8099 (north america) 33-14-906-3980 (international) web site www.conexant.com world headquarters conexant systems, inc. 4311 jamboree road p. o. box c newport beach, ca 92658-8902 phone: ( 949) 483-4600 fax: (949) 483-6375 u.s. florida/south america phone: ( 727) 799-8406 fax: (727) 799-8306 u.s. los angeles phone: ( 805) 376-0559 fax: (805) 376-8180 u.s. mid-atlantic phone: ( 215) 244-6784 fax: (215) 244-9292 u.s. north central phone: ( 630) 773-3454 fax: (630) 773-3907 u.s. northeast phone: ( 978) 692-7660 fax: (978) 692-8185 u.s. northwest/pacific west phone: ( 408) 249-9696 fax: (408) 249-7113 u . s. south central phone: ( 972) 733-0723 fax: (972) 407-0639 u.s. southeast phone: ( 919) 858-9110 fax: (919) 858-8669 u.s. southwest phone: ( 949) 483-9119 fax: (949) 483-9090 apac headquarters conexant systems singapore, pte. ltd. 1 kim seng promenade great world city #09-01 east tower singapore 237994 phone: (65) 737 7355 fax: (65) 737 9077 australia phone: (61 2) 9869 4088 fax: (61 2) 9869 4077 china phone: (86 2) 6361 2515 fax: (86 2) 6361 2516 hong kong phone: ( 852) 2827 0181 fax: (852) 2827 6488 india phone: (91 11) 692 4780 fax: (91 11) 692 4712 korea phone: (82 2) 565 2880 fax: (82 2) 565 1440 phone: (82 53) 745 2880 fax: (82 53) 745 1440 europe headquarters conexant systems france les taissounieres b1 1681 route des dolines bp 283 06905 sophia antipolis cedex france phone: (33 1) 41 44 36 50 fax: (33 4) 93 00 33 03 europe central phone: (49 89) 829 1320 fax: (49 89) 834 2734 europe mediterranean phone: (39 02) 9317 9911 fax: (39 02) 9317 9913 europe north phone: (44 1344) 486 444 fax: (44 1344) 486 555 europe south phone: (33 1) 41 44 36 50 fax: (33 1) 41 44 36 90 middle east headquarters conexant systems commercial (israel) ltd. p. o. box 12660 herzlia 46733, israel phone: ( 972 9) 952 4064 fax: (972 9) 951 3924 japan headquarters conexant systems japan co., ltd. shimomoto building 1-46-3 hatsudai, shibuya-ku, tokyo 151-0061 japan phone: (81 3) 5371-1567 fax: (81 3) 5371-1501 taiwan headquarters conexant systems, taiwan co., ltd. room 2808 international trade building 333 keelung road, section 1 taipei 110, taiwan, roc phone: ( 886 2) 2720 0282 fax: (886 2) 2757 6760 so990810(v1.3) |
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